Power-savvy tool replaces clock-tree synthesis
By Michael Santarini -- EDN, May 17, 2005
EDA start-up Azuro Inc wants to help ASIC designers get a better handle on IC power conservation and ultimately lengthen the runtimes of their wireless applications. Toward that end, the company recently introduced the PowerCentric EDA tool, a power-savvy replacement for clock-tree synthesis that the company claims yields 10 to 20% power savings.
The company’s chief executive officer, Paul Cunningham, says that, in today’s ASIC flow, designers typically perform clock gating during logic synthesis and perform clock buffering during clock-tree synthesis after physical optimization and placement. “You cannot quantify the impact of clock gating on timing and power until you get to the clock tree,” says Cunningham. “It’s a plug-and-pray method; you throw in something based on a sensible rule of thumb and then hope it gives you the best result in the back end.” More often than not, he says, the result is that users have to repeat synthesis through clock-tree synthesis until they get an acceptable balance between performance, area, and power. “It is too hard to do by hand because there are just too many permutations,” he says.
The technology allows users to do clock gating and buffering at points in the design when they used to perform clock-tree synthesis. In the Azuro flow, users input a placed gate netlist, DEF/PDEF, SDC, .lib, and LEF files into PowerCentric. The tool also accepts manually gated or tool-generated clocks. The tool’s Gated Synthesis engine reads the placed gate netlist, rather than RTL (register-transfer-level) code. “Rather than looking at RTL, we look directly at the circuit diagram of the gate level netlist—at the individual flip-flops in the design,” says Cunningham. “From that, we can extract three times more potential gating opportunities, where we can optimize the designs.”
Once the tool finds gating opportunities across the entire chip design, it uses iCTS (intelligent-clock-tree-synthesis) engine to evaluate across the entire design the opportunities and trade-offs, such as the overhead of increased buffering and clustering and their impact on performance and area. The iCTS uses the vectorless SASm static-circuit-estimation technology, which derives the average activity of a circuit in the field without using exhaustive detailed simulation. PowerCentric’s iCTS engine then generates an optimized clock tree, performing buffer insertion, placement, and sizing, in addition to placing and sizing clock gates. The tool removes, resizes, or replaces any un-preserved buffering or clock gating in the input design. The tool in 64-bit configuration currently takes one hour to run for every 100,000 optimized instances. Prices for PowerCentric start at $150,000 for a one-year license.
Azuro Inc, www.azuro.com.
