FPGA physical-synthesis tool claims to know the fastest routes
By Michael Santarini, Senior Editor -- EDN, October 3, 2005
Synplicity boasts that in a single pass its new graph-based FPGA physical-synthesis tool uses inside knowledge of specific FPGA architectures to deliver a 5% to 20% performance improvement over the company's popular logic-synthesis tool. In addition, the company claims, 90% of all routed nets fall within 10% of final timing correlation.
That new tool, called Synplify Premier, will replace the company's Amplify physical-synthesis tool and become Synplify's top-of-the-line FPGA synthesis tool.
The key to the tool's performance boost is its graph-based physical-synthesis engine, said Jeff Garrison, the company's director of FPGA product marketing.
Because FPGAs are prerouted, they limit the paths you can take between two functions. Synplicity has found a way to turn that architectural shortcoming into a design advantage by doing detailed analyses of the interconnect within certain FPGA families, Garrison said. Synplify Premier's graph-based engine has access to that information, which it uses to accurately find the fastest route to interconnect blocks within the FPGA, he said.
Most FPGA physical-synthesis routers, he added, use proximity-based techniques originally designed for ASICs. Proximity-based routers attempt to place functions next to each other or in close proximity in order to reduce the length of interconnect. "But in an FPGA, placing one function right next to another function may not be the fastest route between the two functions," Garrison said. "It's like commuting to work—you sometimes drive a bit out of the way to get to work faster."
In addition, Synplify Premier does not require users to synthesize and floorplan their designs if their designs consist entirely of synthesizable RTL code, Garrison said. Users can feed the tool RTL code, push the "go" button, and watch the tool find the optimum floorplan, placement, and routing. The tool performs synthesis, floorplanning, placement, and prerouting concurrently, with detailed routing performed by the FPGA vendor's proprietary router.
However, designers who are using a hard or firm macro, or who want to tweak the layout, must buy a floorplanner add-on called DesignPlanner, which costs an additional $15,000 to $29,000 over the $34,000 to $74,000 cost of Synplify Premier.
The top-of-the-line version of Premier also features a built-in version of Synplicity's Identify debugging engine and a scaled-down version of the company's Certify ASIC-prototyping tool. The scaled-down prototyping technology allows users to create ASIC prototypes on a single FPGA. This includes the majority of FPGA-prototoyping projects, according to Garrison, because many users employ a single FPGA to test new functionality they plan to add to a design previously implemented in an ASIC. Users will need full-blown Certify if they want to prototype ASIC designs in more than one FPGA.
While the technology is seemingly a breakthrough for FPGA routing, Garrison concedes that it can't be applied to ASIC design because routing is unique for every ASIC.
As of now, Synplify Premier supports three Xilinx device families: Virtex 4, Virtex-II Pro, and Spartan 3. The company plans to support Altera's Cyclone and Stratix devices in an upcoming release. The tool is a free upgrade for customers in possession of current Amplify licenses.
