Synopsys spins new physical model, preps statistical timer
By Michael Santarini, Senior Editor -- EDN, November 7, 2005
In a prelude to announcing a statistical-timing-analysis tool in the near future, Synopsys will announce this week that it has modified its Composite Current Source (CCS) model so that users can perform timing, power, and noise analysis using a single model that is accurate to within 3% of HSpice.
Traditionally, designers have used three separate models for characterizing physical library elements: one for characterizing timing, another for noise, and a third for power. These models have traditionally been table-based WLMs (wire-load models) and more recently NLDMs (nonlinear delay models), which apply a worst-case boundary for timing, power, and noise separately.
These table-based models tend to be too pessimistic in some cases, which can leave performance on the table, or they simply miss the influence of important affects. As processes shrink below 90 nm, timing, noise, and power are all interrelated, and table-based models can't give an accurate account of that, said Rajiv Maheshwary, Synopsys' senior director of product marketing.
"With design challenges of 90 nm and below, there is a shift to use of current-based models rather than a single lookup table with a number," Maheshwary said.
"In the past, the NLDM, for example, was a simple table with cell delay and alpha transition," added Bill Mullen, the company's vice president for engineering, timing, and characterization. "With CCS we are capturing a waveform so we can analyze the driver with arbitrary interconnect resistance and capacitance networks."
Synopsys introduced CCS for modeling timing back in 2004, but has only now extended the technology to include noise and power.
Because of this, CCS models can now capture a slew of interrelated nanometer effects, such as high impedance interconnect, the Miller effect, dynamic IR drop, multivoltage, and temperature inversion, Maheshwary said.
Synopsys claims that CSS has proven accurate to within 2% of Spice for Texas Instruments and to within 3% for STARC, a consortium of semiconductor firms in Japan. CCS models also compile 100 times faster than NLDMs, Synopsys claims.
With vendors such as IBM and ExtremeDA already fielding statistical timers, it behooves Synopsys to protect the market dominance it enjoys with its static-timing tool PrimeTime and try to extend that success to its upcoming statistical engine by devising, proliferating, and seeding the market with its own open model.
However, while Synopsys' NanoChar characterization technology and PrimeTime support the CCS timing model, the company's IC Compiler won't until next month. Also, the company doesn't expect to support noise in NanoChar until March of next year, and says the rest of Synopsys tool suite won't support noise and power CCS models until June of next year.
CCS is open to all comers, including competitors, via Synopsys' established Liberty open-source license. Thus far, no other EDA firms have signed on to use CCS, but library vendors like ARM/Artisan, Virage Logic, and Library Technologies are supporting it. TSMC, Texas Instruments, and STMicroelectronics are also using it, and the effort also has buy-in from STARC, Maheshwary claims.
To help user companies adopt CCS, Synopsys has created guidelines and ASCII screeners, checkers, and parsers.
