Network on chip replaces on-chip bus
By Michael Santarini -- EDN, March 17, 2005
French start-up Arteris SA has released a speedy alternative to traditional on-chip bus systems, introducing an NOC (network-on-chip) system that accommodates multiple asynchronous clocking that many of today's complex SOC (system-on-chip) designs use (Picture). The NOC Solution brings a networking method to on-chip communications and claims roughly a threefold performance increase over conventional bus systems. The SOC Solution will compete against proprietary on-chip bus architectures and commercial, on-chip buses, such as ARM’s (www.arm.com) AMBA (Advanced Microcontroller Bus Architecture) and Sonic’s (www.sonicsinc.com) SiliconBackplane.
Philippe Martin, Arteris’ vice president of marketing, says that the NOC Solution applies a networking concept to on-chip communications. In much the same way a network links multiple computers, the NOC Solution links multiple distributed systems, such as individual IP (intellectual-property) blocks and clusters of functions, reducing the number of traces and, thus, the latency in a design. “There has been quite a bit of research going on in the area of NOC over the last few years, but it has been mostly academic,” says Martin. “We are now offering it commercially.”
The product comprises the Danube NOC IP library, NOCexplorer for deriving an NOC architecture, and NocCompiler for generating SystemC and synthesizable Verilog and VHDL. Martin says that the NOC Solution targets design groups implementing asynchronous-design methodologies using multiple clocks and hundreds of blocks of IP on a single-chip design. For this purpose, Arteris has developed the proprietary, on-chip, packet-based NTTP (NOC Transaction and Transport Protocol). The Danube library, which comprises NIUs (network-interface units), packet-transport units, and physical links, contains the elements for implementing that protocol.
Chip architects use the NOCexplorer tool to perform NOC-topology modeling and derive an NOC architecture. NOCexplorer users designate clusters of synchronous logic using a GALS (globally asynchronous, locally synchronous) methodology. The tool uses NIUs to connect the NOC to cores using on-chip socket standards, such as AMBA AHB (Advanced High-Performance Bus), AMBA AXI (Advanced Extensible Interface), and OCP (Open Core Protocol) 2.0.
Switches from the Danube library control synchronous links between clusters, and GALS from Danube control asynchronous links. NOCexplorer models the system behavior with a dataflow simulation engine. After chip architects derive the optimal NOC configuration for their designs, they use the NOCcompiler to generate synthesizable Verilog, VHDL, or SystemC to implement their designs through the traditional IC-design flow.
NOCcompiler has a rules-checking feature to ensure design consistency across multiple versions, and it also can estimate area at the presynthesis stage. It produces a data sheet of configured NOC units, including a register map. Martin says that STMicroelectronics (www.stmicroelectronics.com) implemented the first design using the NOC Solution. The NOC ran at an operating frequency of 750 MHz on a 90-nm TSMC silicon process, using Artisan libraries and off-the-shelf EDA tools. Prices for the NOC Solution start at $350,000.
Arteris, www.arteris.com.
