System Verilog for the masses
By Michael Santarini, Senior Editor -- EDN, May 16, 2005
Aiming to bring advanced verification languages like SystemVerilog and advanced methods like assertion-based verification to mainstream IC designers, Mentor Graphics this week is introducing its new Questa verification tool.
Questa adds to the company's ModelSim simulation kernel with new engines for assertions, constrained-random testbenches, and code coverage, plus a new feature that monitors the progress of each verification step and attempts to answer the age-old question: How much verification is enough?
According to a 2004 study conducted by research firm Collette International, functional errors constitute the No. 1 cause of IC respins, and this is the main reason design teams have traditionally spent as much as 70% of IC development time trying to verify the functionality of their designs. However, verification also takes a long time because the industry has been slow to come up with standards, advanced tools, and methods to reduce verification times.
Now, with Questa and help from standards group Accellera (coincidentally chaired by Mentor/ModelTech employee Dennis Brophy), users have a commercial tool that allows them to apply newer verification languages and methods to their designs and hopefully reduce overall verification time.
"The industry has reached a turning point," said Robert Hum, vice president and general manager of Mentor's design-verification and test division. "Questa has the right combination of methodology, standards-based languages, tools, and libraries that best close the 'verification gap' in the industry today."
To develop Questa, Mentor engineers started with the ModelSim kernel and modified it to also support assertions, constrained-random testbenches, and code coverage, Hum said.
Mentor developed the Questa technology in-house over the last two and half years, and the tool has been thoroughly field-tested by beta customers, he added. "We tested this tool longer than the last four releases of ModelSim combined," Hum said. "In that time, users haven't been pointing out hard errors or bugs—they've been sharing methodology questions."
Mentor offers two versions of the tool: Questa SystemVerilog for $28,000 (perpetual) and Quasta AFV (Advanced Functional Verification) for $42,000 (perpetual).
Questa SystemVerilog simulates SystemVerilog and Verilog 2001 and has assertion, functional-coverage, and testbench-automation support for SystemVerilog, all controlled in a single kernel.
The tool complies with the emerging IEEE P1800 SystemVerilog standard, including its specifications for design constructs, testbench constructs, assertion, and the DPI (direct programming interface).
Meanwhile, the full version of the tool, Questa AFV, simulates with one kernel Verilog 2001, VHDL, and SystemVerilog, and has assertion and functional-coverage support for SystemVerilog and PSL, as well as testbench-automation support for SystemVerilog and SystemC.
Questa has a setup similar to ModelSim, but to use the tool's assertions, constraint solver, and coverage-analysis features, users need to write assertions into their design and create a testbench that both takes advantage of coverage and makes use of the constrained-random paradigm.
"This requires, of course, investment in creating assertions, which our 0-In [assertion-synthesis tool] can significantly ameliorate, and investment in creating a testbench that has the necessary properties," Hum said.
Questa can run vanilla Verilog without modification, so no actual changes are needed in either the design or testbench, Hum said. "But in that case, users are not taking advantage of the advanced productivity features of SystemVerilog, PSL, or SystemC that Questa offers," he added.
Both tools include a common coverage database that integrates coverage data for transaction coverage, functional coverage, assertion coverage, and code coverage.
Hum is quick to point out that Mentor's MTI ModelSim simulator is not going away with the introduction of Questa. Mentor will continue to develop ModelSim as its standalone simulator, he said, adding that the company will also continue to sell its FPGA-centric ModelSim Designer.
ModelSim SE users can upgrade to Questa AFV for $11,000, and ModelSim SE users can update to Questa SystemVerilog for $7000.
Mentor is also offering methodology training to instruct users on the new capabilities in SystemVerilog and Questa, training on the conversion of legacy testbenches to SystemVerilog, and training on language and tools usage.
Mentor Graphics, www.mentor.com
