IBM makes EDA play, offers commercial statistical-timing tool
By Michael Santarini, Senior Editor -- EDN, June 2, 2005
Making a serious bid to displace Synopsys' PrimeTime static timer as the IC design industry's gold-standard tool for signoff timing-analysis, IBM this week will make its EinsTimer statistical timing tool available commercially. The company claims the tool will improve IC performance by as much as 15% over static tools.
IBM has been using the EinsTimer static tool internally for several years as its own transistor- and gate-level signoff timing tool. In fact, the company has taped out more than 1500 chips with the tool, including ASICs and custom devices like microprocessors, according to Dale Hoffman, director of business development and CTO of IBM's Engineering and Technology Services division.
Over the last few years, IBM researchers have been trying to improve the tool by augmenting it with a statistical engine, he said. The progress of that research effort has received great attention in academic circles and at conferences, with an IBM research paper nabbing the best-paper award at last year's Design Automation Conference.
Experts have deemed the research important because designers have traditionally relied on static timing tools that use worst-case timing models to characterize the timing of circuits. Those models are too conservative and pessimistic and, as a result, typically leave performance on the table, according to the father of the EinsTimer statistical engineer, Chandu Visweswariah, an IBM research staff member who manages the circuit and interconnect-analysis group. Morover, static tools haven't been able to account for process variability that has been a problem since the 180-nm node and is only getting worse with every process-geometry shrink, Visweswariah argues.
"We believe this is going to be a game-changing solution," Hoffman said. "We believe process variability is going to be the next big wave of design problems and is already here."
EinsTimer, with its added statistical engine, applies statistical analysis to critical paths in designs to derive models that are more silicon-accurate than models used in static analysis, Hoffman said. Those models can then be applied to the rest of the paths in the design, improving the design's overall performance by as much as 15% over traditional static timing. "The performance gain you actually obtain will depend on your chip and the length of paths on your chips," Visweswariah said.
The tool's accuracy to silicon has been verified with extensive Monte Carlo analysis, and the tool has been used to verify multimillion-gate designs, Visweswariah added.
IBM will offer the tool as a standalone, silicon-independent EDA product, but prefers it be sold with a services engagement and that it be tied to IBM silicon, because the tool has already been correlated to IBM silicon and used in house. Yet the IBM researchers emphasize that the technology isn't specific to IBM silicon. "We feel we have made the tool such that it will be very easy and minimally invasive for people to integrate into their existing flows," said Visweswariah, noting that the tool accepts industry-standard files.
In the design flow, users will input an LEF/DEF netlist of the design and .lib library-delay models, Visweswariah said. "You also need to understand what are the sources of variation and how the cells in your library have delays that depend on these process parameters," he said.
With EinsTimer, IBM provides a characterization tool that runs a Spice-level analysis on every cell in the library to understand the sensitivity of cell delays to process. That characterization is done only once, unless the library is respun. The characterization tool then outputs a modified .lib file that is in turn used by the statistical tool for analysis.
"Then the statistical tool outputs reports and yield plots to help you understand your design much better," Visweswariah said.
Because the tool supports industry standards in timing, it can be used during optimization as well as for signoff to ensure that the design has a one-to-one correlation with signoff timing, Visweswariah said.
The statistical engine not only removes the pessimism of timing parameters but also helps designers better understand yield, he said. For example, users can employ the tool after they have routed their design and created a clock tree in order to understand sensitivity to metal issues and transistor parameters. "That will give you an idea of how robust your design is, what kind of yield you can expect on a particular design," Visweswariah said. "And then you can modify the design to improve these timing characteristics prior to tapeout."
IBM is not releasing the price of the tool, but Hoffman stated that it "will be competitive."
