Multiprocessor system sports up to four coherent, multi-threaded cores
The nine-stage pipeline architecture of the MIPS32 1004K coherent processing system will support a worst-case 800-MHz base core operating frequency, in a TSMC 65-nm GP process, implementing a two-core, dual-threaded configuration with 32-kbyte caches for each core, as well as the Coherence Manager and Global Interrupt Controller.
By Robert Cravotta, Technical Editor -- EDN, April 1, 2008
MIPS32 1004K coherent processing system is a multithreaded, multiprocessor licensable IP multiprocessor platform that supports up to four single- or double-threaded processor cores connected together through a coherence manager.
The nine-stage pipeline architecture will support a worst-case 800-MHz base core operating frequency, in a TSMC 65-nm GP process, implementing a two-core, dual-threaded (for a total of four threads) configuration with 32-kbyte caches for each core, as well as the Coherence Manager and Global Interrupt Controller.
There are integer (1004Kc) and floating-point (1004Kf) versions of the core, and they both support Revision 1 of the MIPS32 DSP ASE. The design-time configurability of the platform allows designers to size the instruction and data caches, TLBs, scratchpad RAM, and user-defined instructions; however, the configuration must be the same for each core in a given implementation so that the architecture can support SMP (symmetric multiprocessing) operation with SMP-based operating systems, such as Open Source SMP Linux.
The Multicore Coherence Manager can manage one to four single- or dual-threaded cores, and it operates at the same clock rate as the cores (which all operate at the same clock rate also). The Coherence Manager supports cache-to-cache transfers, speculative reads to external memory, and global cache operations. It manages coherency using the MESI (Modified/Exclusive/Shared/Invalid) protocol, and it employs redundant tags to enable L1 cache transfers while minimizing the impact on processing performance. Designers configure and control the coherence scheme through Global Configuration Registers. The platform supports an optional 256-bit interface that can manage fractional clock rate access to an L2 memory controller. The optional I/O Coherence Unit bridges non-coherent I/O peripheral data transfers so that the transactions are coherent within the system; it also supports per-transaction attributes for snooping L1 and L2 caches, non-coherent transactions, and I/O prioritization. The Global Interrupt Controller can route up to 256 system-level and inter-processor interrupts to specific cores or VPEs (Virtual Processing Elements).
The software development environment (SDE) for this platform includes the GNU based MIPS SDE toolchain, the MIPSsim bus functional modeling and instruction set simulator, and the EJTAG and PDtrace System Navigator probe with coherence awareness.
The two initial versions of this core, the integer 1004Kc and the floating-point 1004Kf will be available for licensing this quarter.
