What’s Happens After 10 Nanometers?
By Ed Sperling -- EDN, June 3, 2005
San Francisco -- Intel publicly unveiled for the first time its future plans for chip development beyond 10 nanometers, combining silicon with a number of other technologies that are still in the very early research stages.
The blueprint, introduced at the First International Nanotechnology Conference Thursday, is likely to set the bar for the rest of the electronics industry, which frequently follows Intel’s lead although not necessarily at the same pace as Intel. And while there are many question marks within that statement of direction, it is the most forward-looking statement yet made on the future of semiconductors.
“CMOS will be around in 2015, but there will be many elements around it,” said Paolo Gargini, director of technology strategy at Intel. “Moore’s Law will outlive CMOS, but there will be new nano structures at 10 nanometers.”
Those technologies will include everything from rapid single-flux quantum devices to “biologically inspired” and plastic technologies, as well as optical components and nanoelectromechanical systems (NEMS). Gargini said the integration of these devices will provide a continuation of the scaling that the industry has grown accustomed to, roughly a 70 percent improvement in performance every two to three years. He said new devices will begin entering the mix around 2010 to continue providing that scaling.
How that road map plays out across the rest of the industry is unknown, but there is likely to be far more cooperation on new technologies from places like Europe and Japan than ever before due to the rising cost and complexity of development. And companies like Intel and Texas Instruments are now readily collaborating on pre-competitive technology.
“The more ideas and more input you get, the less likely you are to get broadsided,” said Hans Stork, chief technology officer at TI. “There are two tracks here. One is the same physics as we’ve been using. The other is a new set of applications where new things are enabled. Both are very interesting. Carbon nanotubes add new capability, but we’re not able to harness them yet -- and we may never be able to do that for some of these technologies.”
Stork noted the accuracy of a 20-year road map is always suspect, but he said it does give companies an idea of where to invest. “What we have to do now is consider how much capital is needed to invest. But even when it becomes serious that we are going to back a technology and we know how much of an investment it will require, it’s still a five-year horizon. When you add all of that up for a company, it’s a 10-year effort.”
Dean Freeman, semiconductor manufacturing analyst at Gartner, said that so far the limit on gate lengths in silicon appears to be about 5 nanometers to 10 nanometers. And while limits have been set and then broken in the semiconductor industry, a number of alternatives are beginning to show up including spin-based devices that are driven by single electrons.
“We’re already seeing experimentation with vertical transistors,” said Freeman. “Berkeley and IBM have been working on a dual-gate device. Intel has introduced a tri-gate device. And with nanotubes, you can have infinite gates.”
Freeman noted that Samsung and Motorola both expect to begin using nanotubes in displays within two years. He said nanotubes could show up in five to six years in interconnect technology, as well.
“All of this is within the context of integration of CMOS,” noted Lubab Sheet, nanotechnology analyst at SEMI. “This is more of Moore. A lot of people see the potential to leverage the existing infrastructure with new stuff around it. That makes sense. We’ve already got the manufacturing infrastructure. We might as well use it.”
