Why design engineers need to know about lithography, part 2
By Ann Steffora Mutschler, Senior Editor -- EDN, November 23, 2007
In the quest to account for lithographic impacts in IC design and allow for the continued shrinking of transistor feature sizes, engineering teams can either reduce the wavelength of the laser used to print features onto wafers, and/or increase the numerical aperture of the imaging tool to make the image print clearly on the wafer, as discussed in part one of this two-part series.
As a result, semiconductor manufacturers have moved to lasers with smaller wavelengths: from 436 nm in 1980 to 193 nm in 2001, where lithography tools operate currently. At 248 nm, however, things started to change, as chipmakers began patterning below the wavelength of the light source, which began causing image distortion along with other imaging issues.
However the progression to smaller wavelengths has stalled at 193 nm and although there is work being done on extreme ultraviolet (EUV) lithography to extend the capabilities of the current technology, it is estimated EUV won’t be ready for another 5 to 15 years.
A second was to improve printability of feature sizes is to increase the numerical aperture (NA) of the lithographic imaging tool, with water immersion lithography currently being used.
A third way to shrink feature sizes is through double patterning, which the semiconductor manufacturing industry has embraced. This technique does shrink feature sizes, but requires two passes through the scanner, and breaks an image up onto two masks, with each one containing 50 percent of the features.
Double patterning is a resolution enhancement technique (RET) that effectively doubles the pitch of lithography. The technology was added to the ITRS roadmap in 2006 and is viewed as a leading option to extend 193 nm immersion lithography to the 32 nm process node while using existing tools. Double patterning is also viewed as a bridge to EUV lithography technology, which is not expected to be available for volume production until approximately 2013 or later.
However, double patterning requires overlay limitations, and when you break the mask apart, there will be OPC issues that will make some features more difficult. This is definitely a technique where designers need to get more involved, notes Chris Bencher, distinguished technologist, Applied Materials.
In this arena, one of the efforts underway is by Round Rock, Texas-based photomask provider Toppan Photomasks Inc. and Grenoble, France-based technology R&D organization Electronics and Information Technology Laboratory of the French Atomic Energy Commission (CEA-Leti) which said recently that they will explore double patterning techniques under a joint development agreement.
Even with the challenges, Bencher asserts that “the lithography bottleneck is good for us. There is a bottleneck for printing but there is no bottleneck for patterning.”
Since double exposure involves two etches, more burden of responsibility is shifting to etch and thin films to allow double patterning and spacer mask patterning techniques, he explains.
Further, Bencher also noted the litho bottleneck is good for the company in that Applied recognizes its role in enabling new patterning techniques, “that we are innovative and capable of contributing solutions.” The company also anticipated the role in advance and has manufacturing processes ready to fill the gaps without delay to roadmaps (such as the spacer mask patterning). Technologists at Applied who want to take a more involved role in creating patterning solutions for the industry also have an opportunity to share in development.
Also, “It’s good for Applied because it gives us the opportunity to participate in multi-dimensional collaborations including designers, EDA companies, scanner suppliers, and chip manufacturers,” he added.
In terms of collaborations, lithography simulation is one area that holds promise to make a difference in solving design to manufacturing issues by bring EDA companies and equipment suppliers to the same table.
To this end, Cadence Design Systems’ Roy Prasad, VP of R&D for advanced patterning solutions in the company’s silicon signoff and optimization group reminded that EDA players are no longer dealing just with design – it’s all about post tape-out.
Recognizing the importance of this shift in the industry, Cadence made two significant acquisitions this year when it purchased litho pattern synthesis provider Invarium in July and ClearShape in August. Last year, Cadence also quietly acquired Praesagus Inc., another DFM startup.
“If you look at the overall DFM picture, ClearShape was focused on bringing manufacturing models into the design phase for analyzing layout for electrical issues and to determine more tolerant manufacturing variations,” explained Nitin Deo, group director for DFM marketing at Cadence.
“Then, the Invarium technology comes in to provide more predictable OPC results. The tools are very complementary to each other,” he continued.
The key issue now is how to allow EDA tools to thoroughly understand manufacturing issues. Adoption is still mainly in the high end user segment: IDMs with high end processors, memory suppliers, high end fabless companies focused on mobile applications) over a couple of years now, Cadence has observed. This adoption began at the 65 nm process node and is continuing with thorough analysis and incorporation into 32 nm flows.
Along with lithography simulation challenges, how double patterning will impact the design side of the semiconductor industry is still not known. “There is a lot of investigation studying the impact [of double patterning] and how it would come into the picture in terms of impact on designers,” Deo said. “Some parts are obvious, i.e., layer decomposition. There are 6 double patterning processes up in the air.”
Next year, Deo expects this issue to become clearer but in the meanwhile, R&D is taking place to determine software, hardware and materials aspects.
Another issue impacting design today is the occurrence of lithography-induced electrical variation, as well as stress-related systematic defects. Questions remain as to how that type of data be accounted for in a design methodology and well as the impact on timing.
As well, how lithography-induced electrical issues manifest into timing and leakage power issues is being studied. Cadence said it conducted a study for two of its IDM partners that showed if they took their 65 nm design techniques, and ported them to 45 nm, 20 percent of the timing was off, whereas leakage variation was up to 300 percent, Deo said.
“This is not really EDA anymore. A lot of innovation that is happening is coming from modeling the effects in manufacturing and the impacts at silicon, then putting that into an automated flow, to take this data into the design domain so the designer can use it in a way to get better yielding chips,” he added.
Dr. J. Tracy Weed, director of the manufacturing enabling products group at EDA tool giant Synopsys Inc. agrees that work still needs to be on how lithography results can be utilized within the designer’s world to provide results to customers.
Looking to 45 nm and beyond -- down to 16 nm -- other solutions need to be found for tasks such as model-based chemical mechanical planarization (CMP), he says. Stress needs to be accounted for too. “Among the top issues people are likely to see below 65 nm, stress will be a larger issue than in the past. The effect of stress on variation in a p or n channel device, when you look at the stress proximity, can be substantial. If you are trying to close timing, you can have a big problem,” Weed notes.
Past that, Synopsys is developing a concept called “a virtual manufacturing environment” that takes advantage of lithography simulation, integrated with etch for final pattern definition since lithography is key to what people are struggling with. This environment looks at thermal processes, implants, etc., with the potential going forward to get a truly predictive set of tools, and “that’s really what you want to arm the designer with,” he offers.
Synopsys’ virtualized manufacturing environment is not just lithography simulation, but addresses how to connect it back to a methodology, as Cadence’s execs also called attention to.
A step towards this environment is Synopsys’ PrimeYield tool, which links to place and route tools and is being utilized by leading foundries. The company also has a number of key partnerships with major semiconductor vendors and equipment vendors including Intel, Nikon, NEC and Toshiba and has been giving details throughout the past few years on progress.
“Although there are ‘copy exactly’ practices, everyone knows there are ‘golden reticles’ and ‘golden specs;’ if you look at the ITRS metrics, we are getting down into single nm. The fact that certain illumination tool models have slightly different source uniformity patterns needs to be considered. The more information you can provide from the manufacturing into the design world, the more robust your design is going to be,” Weed said.
Tactically, Synopsys has also made a number of key acquisitions. Sigma-C added tremendous simulation capacity for resist and optical simulation, he asserted, while ISE gave Synopsys device simulation and T-CAD for manufacturing technology, bolstered by its HPL buy.
Ongoing work is happening with foundries and large IDMs, along with semiconductor manufacturing equipment suppliers such as KLA-Tencor, whose inspection tool format is based on CATS – Synopsys’ mask data prep software.
Synopsys also has "a number of things in the works" that it is not able to speak about publicly yet.
In the end, creating the technologies that allow the industry to stay in step with Moore’s Law is pulling a lot of people together that wouldn’t typically interact.
In addition to Synopsys’ work with KLA-Tencor, collaborative work has already begun between Applied Materials and Cadence, although the companies would not give further details except to say that the work was done in the context of an IDM customer.
“2008 will be the beginning of an inflection where you see equipment makers and EDA players ‘actively dating,’” Applied’s Bencher concluded.
