Verify your ac Spice model
By Ron Mancini -- EDN, May 26, 2005
A few years ago, the ac parameters of Spice models were almost worthless; they had little correlation with reality. Time changes many things, and now, many ac Spice models are excellent representations of data sheets and, consequently, ICs. The designer still has to verify each new model before using it to ensure that it represents the IC in the design; the following description systematically breaks down the verification procedure.
The data sheet specifies the op-amp gain for the OPA132 as 126 dB at an output-voltage swing of ±13.5V, with Rl=2 kΩ. The 126 dB equates to an open-loop gain of approximately 2(106). Dividing the single-ended output-voltage swing by the gain shows that the input voltage can't exceed 6.75 µV or saturation can occur. Trying to sweep a 6.75-µV source from 0.1 Hz to 100 MHz is impractical, if not impossible, in the lab; thus, you perform this type of analysis with Spice rather than with measurements (Figure 1). The specifications are for a load resistance of 2 kΩ, and the actual load resistance is 1 kΩ, so the maximum input voltage is limited to 5 µV. The gain plot for the op amp crosses 0 dB at approximately 10 MHz, and following the 10-MHz line down to the phase diagram reveals that the phase margin is approximately 50° (Figure 2).
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The step voltage response can correlate with the phase margin, but you must understand two points before this possibility becomes obvious. First, the loop gain of a buffer-configured op amp is identical to the loop gain of the op amp. Therefore, you can put the op amp in a buffer configuration and use a step input to obtain its step response. Second, the circuit, when you model it as a second-order system with a phase margin of 50°, should have a step response of 16%. The phase diagram clearly shows two poles, thus second-order modeling of this system is appropriate.
The step response in Figure 3 has 17% overshoot, which demonstrates excellent correlation between the phase and step response. The gain/phase curves match the data sheet within a few percent, so you can conclude that this model matches the data sheet and will yield data representative of the IC.
| Author Information |
 Ron Mancini is a staff scientist at Texas Instruments. You can reach him at 1-352-569-9401, rmancini@ti.com.
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I am really surprised that an article from the well known R. Mancini contains such confusing resp. wrong statements.
1.) concerning Fig. 2: A phase margin cannot derived from the open loop response of an op amp, because the term "phase margin" can be applied only to a configuration with feedback
2.) Fig. 3: It must be stated that the step response as shown in the figure applies only to the buffer configuration of the op amp (100% feedback); of course it is not the response of the op amp alone.
3.) Therefore, the statement "First, the loop gain....is identical to the loop gain of the op amp" is purely wrong, since an op amp alone (without feedback) cannot have any loop gain.
Lutz v.Wangenheim - 2005-20-8 04:22:00 PDT -
Ron,
It seems you're hinting at some very interesting methods, but as experts often do, I think you're skipping the why part. Are you saying the step response for other loop gains will be the same as for a unity gain buffer? I would have thought that reducing the feedback, ie increasing the system gain would reduce the overshoot? Also, I could ponder the correlation between 50º and 16% (=1.16?), but it would be nice if you elaborated that for us. A third point not clear: Are you getting gain ; phase curves from the simulation? That would have to be from simulating figure #1, right? The phase response looks like it's going to flatten out at 180º for a bit, which tells me that there is no third pole any where near the second one?
Steve
Steve Ungstad - 2005-26-5 13:52:00 PDT
