Cadence officially jumps back into DRC/LVS
By Michael Santarini, Senior Editor -- EDN, September 12, 2005
Cadence Design Systems is making another attempt to recapture the IC physical-verification market, as this week at its CDNLive! conference it will officially unveil its new DRC/LVS (design rule checking, layout versus schematic) tool, called the Cadence Physical Verification System (PVS).
In addition, the company will also unveil a new pricing model for its First Encounter floorplanner that is tailored to customer budgets as well as a new automatic macro placer for the tool. Finally, the company will announce that it has completed the first steps toward offering designers what the company calls Design Kits—essentially integrated tool suites tailored to particular design applications.
For many years Cadence downright owned the lucrative DRC/LVS market with its tool Dracula. But in the mid 1990s the company lost its lead to first Avanti and then Mentor Graphics, which today still dominates DRC/LVS for digital IC design.
Cadence has since made several attempts to recapture the market, but offerings like DIVA, Vampire, Assura, and Chameleon all failed to gain sizable followings. In June, Cadence confirmed to EDN that it was developing a new DRC/LVS tool based in part on technology it had quietly acquired in 2004 from a Beijing-based EDA firm called eTop. The company, however remained tight-lipped about the details. Not anymore.
PVS employs "a hierarchical geometry-processing engine" from eTop, according to Mark Miller, vice president of business development and marketing for Cadence's DFM (design for manufacturability) division. But Cadence developed the majority of the tool in-house to deal with the increasing number of design rules for sub-130-nm IC designs and to overcome the "throughput limitations" of older tool architectures, Miller said.
The tool overcomes a number of issues in sub-130-nm design that are starting to "break" current tools, he added. "It was becoming very clear to us that as we looked at what we had and what our competitors have versus what our customer needed for advanced designs, there is a need for a much more scalable approach," Miller said.
In particular, Miller said, simply accounting for lithography-adjacency effects, such as the halo effect, is pushing hierarchical processing to its limits. Legacy tools are also dated in that they are optimized for previous computing techniques such as multithreading and symmetric processing. "At a point, adding more machines doesn't improve the time it takes to complete a run," Miller said.
PVS overcomes all those issues, he claimed, thanks to what Cadence calls its "optimizing compiler." "The optimizing compiler looks at three things simultaneously. It looks at the rule deck, incoming data and hierarchical data, and the compute resource available," Miller said.
The optimizing compiler searches the rule deck for localized checks that don't affect other areas. It then looks at the data density of each region of the design layout, including those localized areas, and evaluates the available compute resources. The compiler then partitions the design and distributes the pieces to a series of processing algorithms best suited for verifying particular sections of the design, Miller said.
"The key is keeping everything balanced," said Marc Levitt, vice president of Cadence's DFM group. "If any one of those jobs takes too long because you sent your most compute-intensive block to your slowest 32-bit machine, then you are going to be sitting around for a long time."
The company cites benchmarks that indicate the parallel architecture offers run times that increase in a linear fashion with the size of the design. According to the company, a 4.7-million-instance design with 597 rules took 121 minutes to run on a single CPU, a 29-million-instance design with 751 rules took 447 minutes to run, and a 44-million-instance design with 1604 rules took 750 minutes to run. Time to complete a run improved 10× with 16 CPUs, 20× with 32 CPUs, and more than 40× with 64 CPUs, the company claims.
The architecture is extendable and scalable to add new dedicated processing engines and functions, Miller noted. The tool currently includes dedicated processing engines for width-dependent spacing, latchup checks, antenna checks, and density checks. However, the tool lacks integrated OPC (optical proximity correction) and PSM (phase-shift mask). Those pieces are in development and aren't expected until 2006, Levitt said. Cadence counts Fujitsu as its first PVS customer, but said that company has yet to tapeout an IC with the tool.
The company will offer PVS in several configurations, ranging from a single-CPU desktop system to scalable, parallel-processing configurations with dedicated processing engines.
Budget versions
In addition to PVS, Cadence will also announce new versions of it First Encounter floorplanner tailored for particular customer budgets. Over the last few years, First Encounter has become the flagship tool in Cadence's physical-implementation lineup. The company is now hoping a new pricing scheme will expand its user base further.
The company is offering three price points for its tool. Eric Filseth, vice president of marketing for First Encounter, said the new L-series offers a lower price than today's version of First Encounter and targets lower-complexity designs at 0.25, 0.18, 0.15 microns.
The XL-series, which maintains First Encounter's present price point, targets high-complexity designs at the 130-, 90-, and 65-nm nodes.
The company will also release a highly advanced version called GXL-series in the fourth quarter of this year, with pricing to follow.
The XL and GXL versions will include a new algorithm called MasterPlan that through automatic RTL analysis and user-defined design constraints automatically preplaces design blocks during floorplanning, Filseth said.
"A couple of years ago designers only had to shuffle around a couple of dozen or maybe at most a hundred macros to come up with ideal layout," Filseth said. "Designs today have thousands of blocks, and you can spend weeks trying to get the right mix."
MasterPlan may not be able to come up with best layout possible, but it will help you get close sooner in the design process, he said.
Vertical kits
In addition to PVS and improvements to First Encounter, Cadence is also announcing at the show that it has made the first step toward offering customers design kits for specific vertical markets. "Basically, instead of sitting here in the EDA world and forcing our tools on our customers, we are flipping it around and sitting in the customer world and drawing the right tools to solve real customer problems," said Kurt Johnson, group director of verticals marketing at Cadence.
The company's first vertical offering is the Cadence AMS Methodology Kit, a group of tools common to many vertical markets within the analog and mixed-signal design space, Johnson said. The AMS Methodology Kit includes Cadence's AMS Designer, Spectre, VLM, NeoCell/NeoCkt, VAVO, VAEO, VDIO, and Incisive Unified Simulator. The company will customize the kit and add tools and features to it in order to create kits tailored for specific vertical submarkets within AMS.
While none of the tools in the kit are new, the integration of the technologies is, Johnson said. In addition, new elements include a detailed description of the methodology and a reference design, he said.
"The tools have been enhanced to run on something much more comprehensive and real," Johnson said.
The company has also created a partner-specific design kit with its new ARM Optimization Methodology Kit. The kit includes a number of Cadence technologies like First Encounter floorplanning and layout and RTL Compiler synthesis, but weaves in ARM libraries and tools, Johnson said. For example, the kit includes TSMC's 0.13-micron Sage-X (X-Architecture) and 90-nm 90G libraries.
This kit represents a continuance of the collaboration between ARM and Cadence, which has previously yielded their mutual reference methodology, Johnson said.
