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Sun, AMD, Clearspeed Win Japanese Super Computer Biz

Online Staff -- EDN, November 15, 2005

Advanced Micro Devices (AMD) and Sun Microsystems Inc. said today that the Tokyo Institute of Technology (Tokyo Tech), one is creating Japan's largest supercomputer using Sun and AMD technology

The system is based on Sun Fire x64 (x86, 64-bit) servers with 10,480 AMD Opteron processor cores totaling more than 50 trillion floating point operations per second (teraflops), Sun and NEC storage technologies, NEC's integration expertise and ClearSpeed Technology Inc.’s Advance accelerator boards. Using Sun's N1 System Manager and N1 Grid Engine, the system will be provisioned to support the Solaris 10 operating system as well as Linux.

It will be used to help science and engineering researchers dramatically increase their productivity, according to Tokyo Tech. The institute plans to expand the grid-based supercomputer’s operations to more than 100 teraFLOPS by next spring, which would place it among the top five supercomputers in the world.

"Tokyo Tech's system will be leveraged by a wide range of researchers within the university and throughout the world," Satoshi Matsuoka, professor in charge of Research Infrastructure at Global Scientific Information and Computing Center, Tokyo Institute of Technology, said in a statement. "These researchers are tackling complex problems ranging from analyzing the complex molecular structure of proteins, simulated blood flow diagnosis in human brains, modeling of the generation mechanism of Earth and planetary magnetic field and their long term effects, to nanoscience simulation of carbon nanotubes -- all tasks that require exceptional computing power and experience working with supercomputers."

As planned the Tokyo Tech system will be the world's largest and fastest cluster as measured by core CPU count and peak performance, respectively. It will include more than 21 terabytes of memory and 1.1 petabytes of hard disk storage, again exceeding all competing systems within the Asia-Pacific region. There are planned increases in performance to beyond 100 teraFLOPS with installation of additional ClearSpeed Advance boards (initially from 360 to more than 600) by the time of the system's operation in the spring of 2006.

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