FET biasing targets battery-powered PWM applications
Reference provides constant bias voltage regardless of supply-voltage variations.
Steve Franks, Franks Development LLC, Tucson, AZ; Edited by Brad Thompson and Fran Granville -- EDN, November 21, 2005
Many PWM (pulse-width-modulated) applications, such as Class D audio amplifiers, require symmetric drive circuitry. Comprising complementary N- and P-channel FET devices with gates and sources connected, the textbook CMOS pair in Figure 1 provides a low-impedance path to either the positive or the negative power supply and can directly drive a logic-level N-channel FET. Direct coupling of the CMOS pair to the logic driver works well in PWM systems in which the controlled devices operate at the same voltage as the logic circuits. However, raising the output FETs' power-supply voltage while driving the gates from lower voltage logic results in the P-channel device's remaining in conduction because of the difference between supply voltages.
To achieve an off-state, an amplifier's P-channel FET's gate must go to the positive-supply rail. Complementary-CMOS logic-level drivers can't accommodate the amplifier's high positive-supply voltage, and alternatives, such as using commercial FET drivers and operational-amplifier level-shift circuits, add cost and complexity. You can add an external high-voltage N-channel FET to drive the P-channel- amplifier FET's gate (Figure 2). However, capacitive loading imposes an exponential-rise characteristic on the drive waveform, leaving the P-channel FET in its linear operating region for an extended period and thus limiting switching frequency and causing significant power losses in the cascaded FETs.
Current-generation PWM systems can operate at relatively high switching frequencies and, as Figure 3 shows, allow you to use a dc-blocking coupling capacitor, CB, between the logic-level driver's output and the P-channel output FET's gate. Resistive divider R1 and R2 applies a dc bias to the output FET's gate that's equal to the difference between the output power-supply voltage and the midrail logic voltage. For example, in a 12V Class D PWM audio amplifier driven from a 5V microcontroller, bias the P-channel FET's gate at 9.5V (12V–5V/2). Use the specified FETs for logic-level gate drive as output devices because other FETs don't exhibit nominal IDS characteristics at gate drives of 5V or lower.
Battery-powered amplifiers with resistive-divider output-stage bias introduce an additional complication. As battery voltage decreases, so does bias. Instead, you can use a voltage-reference IC or a zener diode, D1, to provide a constant bias voltage regardless of supply-voltage variations (Figure 4). This technique consumes less power than a purely resistive divider and offers more flexibility in coupling-capacitor selection to reduce waveform droop. Based on Texas Instruments' TPA2010 PWM power-amplifier IC (Reference 1), a Class D audio power amplifier boosts the TPA2010's 2.5W differential output to more than 200W rms into an 8Ω load (Figure 5).
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I thought it might be worth clarifying my earlier comment about this circuit not being reliable at anything but a 50% duty cycle.
If for example you AC couple a waveform with a 50% duty cycle and 5 volts Pk-Pk, the waveform will be 2.5 volts above and 2.5 volts below the DC bias at the gate.
If the waveform duty cycle is 90%,
The peak will be (0.1 * 5V) = 0.5V above the DC bias. The valley will be (0.9 * 5V) = 4.5V below the DC bias.
If the waveform duty cycle is 10%,
The peak will be (0.9 * 5V) above the DC bias = 4.5V.
The valley will be (0.1 * 5V) 0.5v below the DC bias.
If the Gate bias is -2.5 volts in relation to the Source, then
90% peak = -2V
90% valley = -7V
This won't reliably turn off the Fet.
10% peak = +2V
10% valley = -3V
This won't reliably turn on the Fet.
The diode clamp circuit I described in my previous comment, acts as a DC restorer at the source of the FET, and works at any duty cycle except 0% and 100%, without requiring any DC offset circuitry.
Tom Blandino - 2005-27-11 14:33:00 PST -
This is a little more complicated than needed, and doesn't work well when the duty cycle is not 50%.
The simplist way to drive the P-Channel Fet reliably is to connect a resistor and switching diode in parallel across the source and gate of the P-channel FET.
The cathode of the diode goes to the source.
The drive signal is capacitively coupled to the gate as before. The resistor value should give a time constant with the DC coupling capacitor of at least 10 times the switching period.
This circuit guarantees that the off voltage is one diode drop above the source voltage supply, regardless of waveform duty cycle. The on voltage is equal to the drive voltage minus one diode drop.
I meant to say "source to gate" when I submitted this earlier. This is corrected.
Tom Blandino - 2005-23-11 12:30:00 PST -
This is a little more complicated than needed, and doesn't work well when the duty cycle is not 50%.
The simplist way to drive the P-Channel Fet reliably is to connect a resistor and switching diode in parallel across the source and drain of the P-channel FET.
The cathode of the diode goes to the source.
The drive signal is capacitively coupled to the gate as before. The resistor value should give a time constant with the coupling capacitor of at least 10 times the switching period.
This circuit guarantees that the off voltage is one diode drop above the source voltage supply, regardless of waveform duty cycle. The on voltage is equal to the drive voltage minus one diode drop.
Tom Blandino - 2005-23-11 08:44:00 PST
