Universal submodule concept cuts I/O design costs, time-to-market
FPGA technology is at the heart of the universal submodule concept that allows system designers to incorporate unique I/O functionality into a standard mezzanine card format.
By Stephen Cunha, MEN Micro, Inc. -- EDN, November 18, 2008
Embedded systems designers are accustomed to adapting off-the-shelf components to assemble cost-effective solutions for specific needs in small- to medium-volume applications. Unfortunately, some I/O function demands are so unique that even standard varieties of mezzanine cards for VME, PCI, CompactPCI and standalone systems can't readily accommodate them. That need has been the impetus for a universal submodule concept that gives system designers the ability to incorporate unique I/O functionality into standard mezzanine card formats—quickly, easily and affordably—through the use of field-programmable gate array (FPGA) technology with soft-core processors that provide local intelligence.
With this open systems approach to optimizing I/O flexibility, common mezzanine modules executed in one of several formats can be programmed to deliver unique combinations of functionality for I/O-intensive applications, such as test and simulation systems, telecom applications, industrial automation and robotics as well as monitoring and control in mobile applications (See ).
Low hardware costs and streamlined design help system designers realize production-ready products with less lead-time, with less development effort and with less cost. Best of all, the functionality of the submodule and FPGAs is easily updated in the field without any hardware modifications to the mezzanine card, and even transferable to other mezzanine cards if necessary. This reduces concerns about component obsolescence or having to reinvent the wheel for upgrades, because the functionality is not tied to the hardware configuration of the original mezzanine card. The result: Better economy and a faster time-to-market for initial implementation, plus greater longevity and flexibility to adapt to changing conditions over time.
Harnessing the versatility of affordable FPGAs
Whereas a traditional application-specific mezzanine card will have its hardware components configured for its defined purpose, the mezzanine card in the universal submodule concept is equipped with an unformatted FPGA and a soft-core controller to manage these specific functions. That mezzanine card also carries Flash and SDRAM memory, plus standard connectors designed to accept a 67.0 mm x 43.5 mm plug-on module that routes user-defined I/O signals between the FPGA and the I/O connector at the front side of the mezzanine card.
The heart of the concept, in terms of cost-effectiveness, is the formatting flexibility of economical FPGAs. (See sidebar "The improving cost effectiveness of FPGAs") These FPGAs can be formatted with existing intellectual property (IP) cores to create discrete capabilities such as a CAN controller, Ethernet controller, Binary I/O controller, PCI to Wishbone interface, Flash interface, UARTs, pulse width modulation, frequency counters or dozens of other functions. Such IP cores are available on the open market (e.g. www.opencores.org) as well as from board and component suppliers.
By implementing and combining specific cores, the designer can give the mezzanine card the unique functionality required for the application. System designers can easily choose to do this set-up and programming themselves or subcontract it to their component vendor or an independent third party.
There are several benefits to be gained—in terms of time, money and convenience—from this flexible implementation arrangement:
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Readily available standard mezzanine cards can be formatted quickly and easily to accommodate unique I/O configuration requirements.
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The availability and use of existing IP cores makes application development easier than doing it from scratch—even for more complex solutions.
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The ability to upgrade programming on the fly is particularly advantageous for applications that are still evolving or situations where re-programmability, reusability or upgradeability is a key concern.
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The capability of transferring FPGA programming and the universal submodule plug-on cards from one mezzanine card to another—even across the various mezzanine card formats—minimizes the issues of hardware compatibility and hardware component obsolescence.
To satisfy user requirements among different embedded system platforms, MEN Micro Inc. has already designed mezzanine cards for the universal submodule concept in four different industry-standard formats:
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M-Module;
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XMC;
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PMC; and
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Conduction-cooled PMC (ccPMC).
These standard mezzanine cards include 2 GB Flash, up to 8 MB SDRAM and FPGAs ranging from 24,000 to 33,000 logic elements (LE). The hardware configuration of the FPGA is loaded during the boot phase from an external 2 MB NOR Flash, using a complex programmable logic device (CPLD), and is serially-transmitted to the FPGA. The Flash memory contains the source code for a minimum configuration of the FPGA over a PCI bus connection. When the FPGA is programmed with the basic configuration, the hardware configuration itself can be loaded into the second area of Flash memory via the PCI bus. A soft-core processor also implemented in the FPGA provides local intelligence as needed.
The cores inside the FPGA can have totally different functions—from computer I/O such as graphics, Ethernet and UARTs to mobile or industrial communication, up to typical industrial functions such as digital/analog process I/O, motor control, SSI, etc. The functional configuration of the fixed-hardware mezzanine cards can be changed at any time through implementation of different IP cores in the FPGAs. Since I/O functions are realized in the FPGA, the lifetime of the mezzanine card module no longer depends on the availability of commercially available logic components. Even after 10 years or more, the original IP cores can be brought into a new or larger FPGA.
The universal submodule concept supports data transfer rates up to 20 Mbits/second and allows the connection of up to 50 bus participants. The user-defined I/O signals from the FPGA are led to a 50-pin SCSI-2 connector at the front side of the mezzanine card.
The line drivers related to the functions of IP cores on the FPGA are decoupled from the mezzanine card module and are implemented on a 67.0 mm x 43.5 mm USM module that is simply plugged onto the corresponding main module (). The same size plug-on module, connectors and spacing are used on all universal submodule mezzanine cards for interchangeable compatibility. The mechanical set-up of the USM plug-on module layout provides maximum space for additional electronic and mechanical components, in terms of both available surface area and available component height (as defined by the different mezzanine card standards).
An open system solution with a wide-open future
While the universal submodule concept is not an officially established industry standard, it is an open system concept with the complete specification readily available to anyone interested in harnessing the potential this approach has to offer. The key drivers of the concept revolve around a simple design structure, low design and production costs, and ruggedness for harsh and/or mobile industrial environments.
Its specification documents the mechanical and electrical characteristics as well as the environmental requirements for the various mezzanine card main modules and the corresponding USM plug-on modules. To aid in application implementation, a development kit—containing a mezzanine card, a USM submodule, an FPGA package, test hardware with a debug interface and detailed documentation—is available for each of the four different board formats.
With a specification that calls for all components to be qualified from -40°C to +85°C (-40°F to +185°F), plus options for conduction-cooled PMC mezzanine cards, the universal submodule concept is capable of satisfying I/O needs across a wide variety of embedded applications. And with sturdy connectors and soldered components, the physical components used to execute the universal submodule concept can meet application demands for increased shock and vibration resistance in end-user embedded applications.
But it is the commonality of being able to share the USM submodules that plug onto the mezzanine boards and to port the FPGA programming from one card to another that gives this concept the flexibility to be expanded to other mezzanine card formats and applications in the future.
Individuals interested in learning more about the universal submodule concept can download the complete specification by visiting www.menmicro.com/download/default.asp?prod_dl=20US00-00&lang=1
| The improving cost effectiveness of FPGAs |
 The declining costs of FPGAs have allowed the universal submodule concept to turn that old purchasing adage ("You can have it fast, good, or cheap—pick any two.") on its ear. Recent improvements in FPGA cost-per-logic-element have helped FPGAs rival the cost efficiency of reduced instruction set computing (RISC) and complex instruction set computing (CISC) procesors, without the attendant lead-time for production and implementation. And once programmed, the FPGA and its soft-core processor replicate the functions of an application-specific integrated circuit (ASIC), yet still offer the versatility of being able to be reprogrammed (See ).Whereas, little more than a decade ago, an FPGA with 100,000 logic elements was $1,000, today's comparable solution is approximately $100. And that same FPGA delivers more than five times the logic elements (gate equivalents) of a 68000 microprocessor with 68,000 transistors (15,000 gate equivalents). Another economic advantage of the FPGA approach is that you need to pay only for what you need. Unlike standard processors that might use only a fraction of their capability in a given application, FPGAs can be selected and programmed according to the number of logic elements required for the specific application. That means not having to pay for unnecessary excess capacity, yet still having the future flexibility to upgrade functionality at a much lower cost. |
| Author Information |
 Stephen Cunha is Vice President of MEN Micro Inc., headquartered in Ambler, Pa. Prior to joining MEN Micro, Stephen worked in sales and business development for Motorola's embedded computer business for twelve years. He received multiple awards at Motorola and was twice awarded Motorola's Pinnacle Award for Achievement. He holds a Bachelor of Science in Electrical Engineering from the University of Virginia. Stephen's email address is Stephen.Cunha@menmicro.com.
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