EDA Startup Launches First Tool
Online staff -- EDN, May 23, 2005
EDA startup Berkeley Design Automation Inc. today launched its first tool – an analog/RF integrated circuit verification tool to address the major verification challenges in the design of high-performance analog/RF ICs.
The Santa Clara, Calif.-based company’s technology is based on research conducted by the founders at the University of California at Berkeley and the University of Illinois, and is meant to allow the characterization of nonlinear, stochastic, time-varying behavior of complex analog and RF circuits.
Products using this technology provide very accurate predictions that dramatically reduce the need for silicon respins, the company purports.
Berkeley DA also announced a noise analysis tool for circuits containing phase-locked loops (PLLs) called PLL Noise Analyzer, meant to accurately analyze noise before tape-out and reduce silicon respins.
The company was founded in 2003 by Amit Narayan, VP of engineering, and Amit Mehrotra, CTO. The two conducted doctoral research together at the University of California at Berkeley. Mehrotra’s Ph.D. thesis topic and his research at the University of Illinois set the foundation for the company’s stochastic nonlinear circuit analysis technology to allow modeling of the nonlinear, time-varying behavior of circuits at the transistor level.
“Analog circuits are pervasive today, even in the most ‘digital’ of designs,” explained Ravi Subramanian, Berkeley Design Automation’s president and CEO in a statement.
“Our customers have told us that the greatest challenge in the design process today is to reduce the rate of silicon spins required to achieve volume production for these analog-rich ICs,” he continued.
“Berkeley Design Automation has successfully delivered to the market a new generation of IC verification technology that has been customer-validated to provide greater predictability and certainty to the design of these complex ICs,” Subramanian added.
Dealing with the nonlinear and stochastic behavior in analog circuits is a major challenge for designers because the analog circuits not only generate noise internally, but they are also extremely sensitive to noise generated by other circuits in an SoC, the company said.
Existing analog verification tools lack the circuit analysis technology required to accurately analyze noise when operating in a nonlinear time-varying environment. For this reason, designers are often forced to use silicon iterations and a variety of approximation methods to analyze noise in order to minimize noise problems.
“Noise and nonlinearity are becoming the limiting factors in the design of high performance analog and mixed signal circuits,” said Abbas El Gamal, professor of electrical engineering and director of the information systems lab at Stanford University.
“The increased performance demands and circuit complexities make the noise analysis approaches used in traditional tools grossly inaccurate,” he continued.
