Processor options keep expanding
By Robert Cravotta -- EDN, May 31, 2005
The tradition of announcing processor families and upcoming architectures continued at this year’s Spring Processor Forum held in San Jose. Tom Halfhill, senior analyst for Microprocessor Report, pointed out that extreme performance, such as from Elixent (www.elixent.com) and Silicon Hive (www.siliconhive.com), as well as integrated DSP functions and configurable cores are becoming mainstream. The following summarizes some of the forum’s announcements and presentations.
ARC’s (www.arc.com) floating-point announcement supports single- and double-precision operations on the ARC 600 and 700 processor cores. The extension requires minimal additional silicon area because ARC engineers reused many of the structures in the pipeline and because the hardware acceleration comprises only the most frequently used portions of the IEEE-754 floating point software library. The floating point extensions cover single- and double-precision multiplication, addition, and subtraction and a fast-storage instruction for 64-bit, double-precision values. To use floating-point operations beyond this set requires software emulation.
AMCC (www.amcc.com) announced the architecture for the 440EPx and 440GRx PowerPC processors that will be available for sampling late this year and have production availability in mid-2006. The 440EPx expands on the 440Ep architecture by supporting a clock rate of 667 MHz and by including a 32/64-bit DDRII SDRAM controller with ECC, an external peripheral bus, USB 2.0 host and device controllers with one PHY (physical layer), a 1-Gbps Ethernet MAC (media-access controller), and an optional on-chip IPSec/SSL (Internet Protocol Security/Secure Sockets Layer)-acceleration engine. The 440GRx is similar to the 440EPx except that it includes no USB support.
ARM (www.arm.com) announced the AudioDE (Audio Data Engine) core features, including the use of the OptimoDE technology. The AudioDE uses a configurable dual Harvard architecture with 16- and 24-bit datapaths as well as dual data memory with dual address generators. The bit-stream-processing extensions to the ALU support bit extraction, manage stream pointers, and allow out-of-order bit-stream access. The AudioDE core uses 35,000 to 42,000 gates. Espico (www.espico.com) is the lead software partner for audio codecs for the ARM OptimoDE Audio Edition technology.
Cambridge Consultants (www.cambridgeconsultants.com) presented its new 32-bit XAP3 soft processor core that supports modeless mixing of 16- and 32-bit instructions for better code density with no performance degradation. The core supports privileged modes to prevent user programs from corrupting the operating-system kernel, and it includes hardware support for position-independent code. The core is available in Verilog RTL and uses 40,000 to 50,000 gates supporting clock frequencies as high as 100 MHz.
Ceva (www.ceva-dsp.com) announced the Ceva-X1621 VLIW/SIMD (single-instruction multiple-data) DSP that it based on the Ceva-X1620 integrated with a configurable cache-memory subsystem. The system provides support for local memories and two levels of cache, and it supports multiple cache- and local-memory sizes. The local memories allow applications to attain deterministic performance, and the caches simplify software development for code that requires no hard determinism. The cache supports 2-D prefetches and 2-D DMA transfers to improve performance of video and image processing. The memory-management unit supports supervisor and per-page protection and unrestricted mapping of local memories and noncacheable areas with varying page sizes.
Elixent announced the D-Fabrix Version 2.0 generation of the company’s reconfigurable-algorithm-processor core, which comprises a fabric of ALUs and dynamic signal routing. The proposed changes to the D-Fabrix architecture resulted from Elixent’s analysis of how its customers were using the fabric. The new architecture supports improved bit extraction and bitwise logic by adding structures outside the ALUs that support bitwise operation. Improving the wiring structure around the switching multiplexes improves the routing efficiency and reduces congestion. These changes reduce ALU counts and critical paths to implement algorithms and provide as much as a twofold improvement in performance density over the previous generation. The company compiled the D-Fabrix v2.0 core to multiple 0.13-nm processes, and a tool chain is available to support the core.
MIPS (www.mips.com) announced the MIPS 24KE core family that adds DSP-application-specific extensions to the 24K core. The 24KE family comprises the 24KEc base integer core; the 24Kef, which includes a full floating-point unit; the 24KEc Pro, which includes MIPS’ CoreExtend interface; and the 24KEf Pro, which includes the floating-point unit and CoreExtend interface. MIPS added the floating-point unit without affecting the core’s clock rate or the ALU’s instructions. MIPS minimized the increase to the core’s area from the floating-point unit by reusing the adder and shifter. The core will be available for general release this summer.
Raza Microelectronics (www.razamicroelectronics.com) presented its XLR processor, which combines eight MIPS64 XLR cores into one processor subsystem. The core microarchitecture relies on a 10-stage, four-way-multithreaded, single-issue engine to achieve and maintain an operating clock rate as high as 1.5 GHz. The system can maintain as many as 32 threads across the eight cores. The 2-Mbyte L2 cache has eight banks and is fully cache-coherent. Point-to-point subsystem interconnects use no buses to maximize data bandwidth for the distributed-memory and peripheral interconnects as well as the messaging network between the cores. The security-acceleration engine comprises four crypto-cores that can perform 10-Gbps bulk encryption. The XLR processors are available now.
Xilinx (www.xilinx.com) announced Version 4 of its 32-bit MicroBlaze soft processor core that targets the company’s FPGAs. MicroBlaze’s new features include an IEEE 754–compatible, single-precision floating-point unit, three new pattern-compare instructions to augment branch- and string-compare instructions, and a configurable hardware multiplier to reduce gate count. The MicroBlaze also supports new debugging logic that allows developers to insert instructions into the pipeline and access anything that instructions can access. The debugging logic uses a packetized data-transfer protocol. The MicroBlaze Version 4.0 is available now and is available with Xilinx’s embedded development kit 7.1i.
