ST touts certified reference design flow
The semiconductor giant said it has achieved significant productivity gains on multiple projects taped out with an advanced electronic system level (ESL) flow that includes tools from Atrenta, Mentor Graphics and Calypto.
By Ann Steffora Mutschler, Senior Editor -- EDN, June 10, 2008
Aimed at complex designs for next-generation consumer electronics equipment and following successful tape-outs of more than a dozen ASIC designs with productivity gains from four to 10 times compared to traditional methods, Geneva-based semiconductor giant STMicroelectronics Monday announced the deployment of a certified electronic system level (ESL) SoC reference design flow, which has been adopted and internally distributed.
ST said it is meeting increasing demands from industry leaders in consumer markets for complete system-level design platforms that integrate digital and RF/mixed-signal technologies, and that a number of ST products have been developed using this reference design flow, including a 2-megapixel YUV CMOS image sensor and a highly integrated image processing hardware accelerator for mobile phones.
This integrated ESL reference design flow for complex digital CMOS designs combines high-level synthesis, sequential equivalence checking, power exploration and lint checkers that look for errors in code construction, thereby providing a complete methodology from ANSI C++ to RTL including certified integration ST's certified RTL-to-GDS2 design flow.
Also, ST noted that the reference flow is the result of more than three years of close collaboration with leading EDA providers for each of the core ESL technologies. Specifically, ST’s flow is integrated with Atrenta’s SpyGlass tool for RTL lint checking and power analysis;Mentor Graphics’ Catapult C synthesis tool; and Calypto Design Systems' SLEC equivalence checker that provides synthesis from pure ANSI C++ to RTL and formally verifies that the resulting RTL implementation is functionally correct. The flow includes: RTL lint sign-off; power estimation and exploration; C-to-C formal equivalence checking; C-to-RTL formal equivalence checking; SystemC model generation; and C-to-RTL high-level synthesis, thereby minimizing risk and shortening design cycles with 'real-world' productivity gains of between four and 10 times.
ST also said it is using its design and verification flow for RF/mixed-signal ICs to accelerate the development of sophisticated mixed-signal chipsets used in multi-band, multi-format wireless products; the RF/mixed-signal design flow is based on Agilent Technologies' Advanced Design System (ADS) software and Mentor Graphics' Catapult C synthesis technology.
In other recent ST news, the company announced last month that to strengthen links with Chinese education and research communities, it will offer Chinese universities access to ST’s most advanced CMOS processes for academic and research purposes through IC broker Circuits Multi Projects.
