LSI Logic releases SERDES-centric structured ASICs
By Michael Santarini, Senior Editor -- EDN, March 16, 2005
The latest version of LSI Logic's RapidChip structured-ASIC technology targets high-speed serial applications in the computing, communications, storage, and embedded-systems arenas.
The new RapidChip Xtreme2 features 12 "slices," essentially design layers with a mix of hardwired functions and programmable-logic blocks, all implemented on 110-nm process technology, said Thomas Colino, director of the RapidChip Platform Architecture.
The family focuses on bringing increased SERDES (serializer/deserializer) support to LSI's high-speed product lineup, by integrating up to 48 SERDES, up to 5 million usable gates, 3.7 Mbits of RAM, a MatrixRAM internal memory architecture, and support for popular external memory interfaces such as DDR2 and QDR.
In the Extreme2 family, LSI offers six slices supporting GigaBlaze SERDES, two slices supporting both GigaBlaze and Hydra, and four more solely supporting Hydra.
Whereas GigaBlaze tends to target high-speed applications, the Hydra SERDES tends to be more flexible, Colino said. "Some of the heavier-weight compute protocols, such as PCI Express and 4-Gigabit Fibre Channel, are not supported in Hydra but are supported in GigaBlaze," he said. "Some comms-specific protocols like SAS [serial-attached SCSI] are supported in GigaBlaze but not Hydra."
The slices that make up the Xtreme2 family also support standards such as Gigabit Ethernet, 10-Gigabit Ethernet (XAUI),) InfiniBand, CX4, Serial RIO, SGMII, SPI4.2, SPI5, SATA, and HyperTransport.
