Structured-ASIC option reaches 45-nm node
The company claims the Nextreme2 product line offers density up to 20 million ASIC gates, up to 30 Mbits of SRAM, and up to 1288 configurable I/Os in a family of devices that can reach 700-MHz operating frequencies.
By Ron Wilson, Executive Editor -- EDN, August 4, 2008
Structured-ASIC pioneer eASIC announced today a family of fast-turn ASIC products at 45 nm, combining the zero-NRE (non-recurring expenses) and six-week turnaround of their via-programmed architecture with the performance, density, and power characteristics of the industry's most advanced production node. The company's Nextreme2 product line is claiming density up to 20 million ASIC gates, up to 30 Mbits of SRAM, and up to 1288 configurable I/Os in a family of devices that can reach 700-MHz operating frequencies based on the delay in 10-logic-element chains.
The Nextreme2 architecture, like previous eASIC designs, combines an underlying layer of FPGA-like logic cells—based on look-up tables (LUTs)—with an interconnect structure that is entirely configured in one via layer. The eASIC manufacturing process mass produces and banks wafers that have been completed up to this via layer. In response to a customer order, eASIC develops a via mask that configures the devices to the customer's netlist and then completes manufacturing of the specified number of wafers. Thus the time from tape-out to chips in hand can be a matter of weeks, and eASIC can waive the NRE charges, absorbing their upfront costs into the unit price of the packaged chips.
The architecture gives up some density and speed relative to a cell-based SOC in the same process node, of course. But because it does not use SRAM-based interconnect switching, it is significantly denser, faster, and lower in power than SRAM FPGAs at the same process node. The company claims, for example, that the Nextreme2 family offers roughly twice the logic capacity of the non-field-configurable Altera HardCopy IV product family, at one quarter the die area. And unlike FPGAs, the chips can employ a variety of aggressive power-management techniques.
The Nextreme architecture was first used in a 90-nm family fabbed at Fujitsu. There are about 120 design wins for the 90-nm Nextreme to date, according to eASIC, including chips created for fabless semiconductor companies and resold as ASSPs, original ASIC designs, and FPGA cost-reductions.
Backed by about $80 million in investment by, among others, Khosla Ventures and Kleiner Perkins Caufield and Byers, eASIC chose to go directly from deployment of its 90-nm Nextreme product to development of a 45-nm product at Chartered Semiconductor. The company chose Chartered, according to president and CEO Ronnie Vasishta, because that foundry provided earlier access to the 45-nm process node than could Fujitsu.
Recognizing the importance of energy management to many of its target markets, eASIC focused significant design resources on this aspect of the Nextreme2 design, according to Jasbinder Bhoot, senior director of marketing. At a microarchitectural level, designers removed the ability to use the SRAM cells in the LUTs as bulk memory, reducing the size of the logic cells and, more importantly, their leakage. Instead, the architects inserted fast 512-bit register files in the logic fabric at intervals. But the majority of the SRAM on the devices is grouped into 36-kbit true dual-port configurable blocks. This clustering allowed the team to use a separate supply voltage for the memory arrays, while still meeting their 600-MHz speed requirements with low-leakage transistors, significantly reducing both static and dynamic power dissipation in the SRAMs.
The chip architecture provides for unused logic cells to be permanently power-gated by the same via mask—V4—that the architecture uses for logic configuration. This capability combines with via-based buffer selection to give nearly the same flexibility as dual-threshold cell-based design in fine-grained control over leakage-timing tradeoffs. As an additional step, the architecture provides for clock-gating with 16-flop granularity—without resorting to synthesizing clock nets using the logic cells—over the whole logic array. Finally, the user may select 1.0, 1.1, or 1.2V core operating voltage, depending on the performance needs of the design.
Such aggressive tools as dynamic voltage-frequency scaling and dynamic power-gating are not supported. But Bhoot points out that the devices achieve their target performance in the LP version of Chartered's process, and achieve their leakage goals without resorting to a high-k/metal-gate option. The underlying chip design is quite conservative, relying on the raw speed and low dynamic power of the 45-nm process rather than on aggressive circuit-design techniques.
Other than memory, the only diffused IP in the Nextreme2 family is in the 6.5-Gbps configurable transceiver I/O structures in the transceiver versions of some of the larger family members. The chip architects decided against hard DSP macros, according to Vasishta, simply because building MAC (multiply accumulator) circuits in the logic fabric gives excellent density, and the same speed that the chip could have achieved with hard MAC macros. There is considerable third-party soft IP, including Tensilica processor cores without royalty and certain ARM cores at reduced royalty fees. The company also has video codecs and other complex IP, as well as complete SOC configurations for specific applications, based on the original Nextreme architecture.
The design flow for Nextreme2 follows the pattern of previous eASIC offerings, relying on a set of proprietary design wizards to prepare RTL for Magma Design Automation BlastCreate synthesis and placement, followed by eASIC routing and configuration. Once the routed netlist reaches this stage, eASIC produces GDS-II for the Via-4 via map, and runs a set of wafers to completion.
Bhoot says that eASIC has silicon in hand on Nextreme2, and will do tapeouts in this quarter for the first customer designs. General release to all customers will be in the fourth quarter of this year.
