DC-accurate, 32-bit DAC achieves 32-bit resolution
A DAC circuit sums two 16-bit PWM signals via solid-state switches to achieve 32-bit resolution.
W Stephen Woodward, Chapel Hill, NC; Edited by Martin Rowe and Fran Granville -- EDN, October 30, 2008
Some applications, such as ADC testing and calibration, require a DAC with extremely good resolution, monotonicity, accuracy, and resolution. In these categories of performance, the circuit in Figure 1 is hard to beat. Its typical specifications follow:
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Resolution=32 bits=3×10–10=1.2 nV=192 dB.
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DNL (differential nonlinearity)=27 bits=400 nV=162 dB.
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INL (integral nonlinearity)=22 bits=1.6 µV=130 dB.
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Full-scale accuracy (untrimmed)=11 bits=±2.5 mV=66 dB.
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Zero accuracy=23 bits=±500 nV±10 nV/°C=140 dB.
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Ripple and noise=21 bits=2 µV p-p=128 dB.
The basis of the DAC’s 32-bit resolution is the summing of two 16-bit PWM signals by analog switches S1 and S2 and precision resistor network R2 through R6. The DAC’s monotonicity and DNL are theoretically infinite, and, in practice, the only limit is the 1-to-216 ratio of R2: (R6+R5+RS2-ON) and R3: (R6+R4+RS2-ON). Typical accuracy of 0.1% resistors yields a DNL of approximately 0.1 ppm=27 bits.
The less-than-0.1Ω output impedance of the AD586 reference and the 130-dB CMR (common-mode rejection) of chopper-stabilized “zero-drift” amplifier A1 mostly limit INL. R7 suppresses a potential contribution from asymmetry in RS1-ON, yielding the typical INL of approximately 0.3 ppm=22 bits.
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Zero-accuracy and output-noise specs are at the low-microvolt level because of the excellent specifications of the LTC1151 A1 and A2 op amps and the charge-injection performance of the MAX4053A S2: approximately 0.4 ppm, or 23 bits.
The precision of the AD586L 5V reference, which is ±500 ppm untrimmed, limits absolute accuracy. If your design requires greater accuracy, then you can use an Analog Devices simple trim circuit to further tweak it. There’s nothing critical about the suggested 200-Hz PWM cycle. You need to change only R1 and C1 to accommodate any convenient frequency. How closely the R1C1 time constant matches the PWM-cycle time determines the settling time of the A1-S2-A2 synchronous “zero-ripple” integrate-and-hold filter, and can be as fast as one cycle if the match is exact.
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Figure 1 download does not work, neither with IE nor FireFox, and possible all your PDF Figures do not work.
Peter Meier - 2010-17-6 11:15:14 PDT -
Al, I wondered something similar, but after hard thinking it became clear. S2 is either pulling S1's +ve input down or its -ve input up.
The effects are matched (by the R2/R3 matching), so think of it as a continuous pull-down of the +ve pull-up, and a matched pull-up of *both* inputs during part of the cycle.
Once you see that both inputs to S1 are pulled up by the same amount and for the same portion of the PWM cycle, you can see that it doesn't matter when S1 switches; the lsb effect of S2 applies equally to both inputs.
I was stressing about the phase relationship between S1 and S2 until I figured that detail out.
Robert Shipman - 2009-24-11 13:55:00 PST -
While trying to understand the math of the summing resistors I suddenly noticed that if the High order DAC has zero loaded into its 16 bits that PWM will be zero and the S1 switch will be at zero. Thus the lower dacs output would not be seen by the integrator. Am I missing something here?
Al Welch - 2009-12-9 11:55:00 PDT -
This circuit and specs require a sanity check. The claim "DC accurate, 32 bit DAC.." is fraught with technical inaccuracies and misconceptions.
We are led to believe that the circuit is hard to beat. Simply using better precision resistors and a better zener would give better specs. In fact all components here can be bettered. Then we are told that "the DAC's monotonicity and DNL are theoretically
infinite". This is nonsense because
as long as the circuit is above absolute zero there will always be Johnson noise limiting a DAC's resolution. I doubt that one
can actually measure a resolution of 1.2 nV when the stated Ripple and noise is a thousand times greater !.
Furthermore we are led to believe that a 32 bit DAC can be constructed with 2x16 bit DACs. This can be done only if the DACs have 32 bit monotonicity and linearity. There is no such 16 bit DAC on
the market. A further limitation is not only the resistor matching but also the switch non-linearity with signal level and temperature and the
dielectric absorption of the capacitors.
This circuit has no "32 bit" spec as the title claims.
Wild claims of this nature should be verified by an independent laboratory with actual data and "theoretical limits" are signs that the author
lacks basic electronics fundamentals.
Elio Mazzocca - 2008-7-11 16:57:00 PST -
A very interesting circuit. Stephen Woodward is a very clever and innovative designer. I tried to simulate it in LTSpice but the filter section does not seem to work. Perhaps i am doing something wrong but I can''t see what the problem is. Has anyone else built the circuit or successfully simulated it?
Randy Evans - 2008-7-11 09:10:00 PST
