Making the transition from bit banger to gigabit guru
As high-speed serial interconnections infiltrate technology, system designers face a series of new signal-integrity problems to manage.
By Eric Bogatin, PhD, Bogatin Enterprises, Bill Hargin, Mentor Graphics -- EDN, September 18, 2008
Interconnects are not “transparent” to digital signals and haven’t been for more than 25 years—since the end of the 20-MHz-clock-frequency regime. High-speed onboard buses drove the lexicon of signal integrity into the vocabulary of every board designer. For that reason, the design guidelines for digital products today all use controlled-impedance boards, terminate all lines, avoid branched routing topologies, reduce inductance of the return paths, and use low-impedance power- and ground-distribution networks.
In the last few years, the proliferation of high-speed serial links, such as PCIe (peripheral-component interconnect express), SATA (serial-advanced-technology attachment), and InfiniBand, has brought with it a new set of challenges that pushes designers into a new regime of signal-integrity problems. This article focuses on four critical problems that confront designers in this new world—frequency-dependent losses; impedance discontinuities, especially from surface pads and vias; intrapair skew; and channel-to-channel crosstalk—and a few tips and tools that will help alleviate some of the pain.
As bit rates increase, the option of relying on luck in the design process decreases proportionately. Successful high-speed-serial-link design must now recognize these problems and leverage the design, materials, and technology approaches to eliminate them right from the start.
The bandwidth of a high-speed serial link, the highest sine-wave-frequency component in the signal, can be as high as 2.5 times the bit rate, which corresponds to the fifth harmonic of the highest bit-transition rate. For example, a PCIe Generation 2 signal at 5 Gbps can have a bandwidth as high as 12.5 GHz. At these frequencies, the interconnects themselves cause four special problems that you must avoid to navigate safe passage.
The first step in avoiding these problems is to recognize them. The second step is to identify their root cause and establish design guidelines to avoid or minimize them. Although design guidelines tell which knobs to tweak and in which direction, an accurate simulation tool that includes these effects is essential to navigating safe passage through design, balancing the trade-offs between cost and performance gain, and meeting acceptable performance specs.
Frequency-dependent loss
As a signal propagates down a board trace, frequency-dependent losses from the conductor and dielectric materials attenuate higher-frequency components more than lower-frequency components. Skin-depth effects constrict the cross section of the trace through which current flows, increasing the series resistance of both the signal and the return paths. This series resistance increases proportionally to the square root of frequency. The motion of dipoles in the dielectric material causes a leakage current between the signal and the return paths that increases proportionally to the frequency. As the dipoles rotate in the electric field of the signal, the leakage current and the associated loss increase proportionally to frequency.
Both of these effects contribute to higher frequencies seeing more attenuation than low frequencies. As a fast-rising edge propagates down the line, fewer high-frequency components remain in the signal, and the rise time increases. This rise-time degradation is the chief cause of ISI (intersymbol interference), which results in the collapse of the eye and deterministic jitter. For example, the losses in a 30-in.-long, 5-mil-wide, 100Ω differential pair in FR4 dramatically degrade the rise time of a PCIe Generation 2 signal at 5 Gbps. One bit affects the next bit so much that the eye nearly closes (Figure 1).
Unfortunately, you have only two design knobs to tweak to improve the performance: Increase the line width of the traces and increase the dielectric thickness to preserve the 100Ω impedance or use a laminate material with a lower dissipation factor than FR4. You should also consider decreasing the interconnect length, but this approach is rarely an option.
If conductor and dielectric losses, which increase monotonically with frequency, dominate the rise-time degradation, two important signal-processing techniques can bring back the original shape of the signal’s spectrum. If the problem is losses at higher frequency, then add pre-emphasis—that is, extra high frequency to the original signal. Alternatively, you can use de-emphasis—removing some of the transmitter’s low-frequency components. De-emphasis consumes less power and has less impact on crosstalk than does pre-emphasis.
Finally, if you know the transfer function of the interconnect, you can employ equalization—adding frequency-dependent gain at the receiver to balance the losses in the line. The combination of pre-emphasis or de-emphasis and equalization can extend the life of low-cost FR4 boards with narrow lines. These signal-processing techniques can overcome even –30 dB of frequency-dependent attenuation.
Impedance discontinues
The signal propagating down an interconnect sees an instantaneous impedance each step along its way. When this instantaneous impedance changes, some of the signal reflects, and the transmitted signal distorts. With multiple discontinuities, the reflected echoes can reach the receiver and cause ISI. The solution to this problem is to minimize impedance discontinuities. Two structures create the biggest discontinuities: surface pads for dc-blocking capacitors and through-hole vias. The dc-blocking capacitors enable drivers with a large common signal level to interface with receivers that can’t tolerate a dc offset. Any capacitance greater than approximately 1 nF is enough to keep the series impedance low. However, unless you take care, the mounting pads of the capacitor create an impedance discontinuity on the surface trace. The solution is to use the smallest body-size capacitor you can afford, such as an 0402, and to reduce the size of the pads to the minimum acceptable for assembly operations. In some cases, removing the plane underneath the pads and capacitor to create a “shadow” or “relief hole” in the plane can minimize the impedance discontinuity. This trick often matches the impedance of the pads and capacitance to the 50Ω of the surface trace.
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The impedance discontinuity of a through-hole via is a more insidious problem. With through-hole technology, a barrel through the entire board connects any two signal lines on different layers. If the layers are buried in the middle of the board, the barrels above and below the signal layers act as stubs. If the stubs are shorter than approximately 50 mils, they look capacitive and slow down the edge of the signal, causing rise-time degradation and ISI. If they are longer than 50 mils, they may act as resonators and cause excessive scattering of signals at or near the resonant frequency. A stub that is 200 mils long has a resonant frequency of approximately 7.5 GHz—well within the 12.5-GHz bandwidth of a PCIe Generation 2 signal (Figure 2).
You can combine design and technology to address via discontinuities. The first step is to minimize the capacitance of vias by removing nonfunctional pads on inner layers, increasing the antipad clearance holes, and minimizing the size of capture pads on the surfaces and on signal layers. You can minimize stub lengths by restricting layer transitions and minimizing the total board thickness. If the stubs are still excessively large, backdrilling can remove the residual barrel. Alternatively, you can implement other via technologies that do not create stubs. These technologies include blind or buried vias and high-density-interconnect microvias that you fabricate by laser drilling. These microvias are the shortest, lowest-capacitance, and most transparent vias available.
Intrapair skew
All high-speed serial links use differential signals. Two independent signal paths carry each half of the differential signal. The pure differential signal from even the best driver can degrade into a common signal if any asymmetry exists between the two lines of the pair. The greatest source of asymmetry is time-delay skew between the two lines. The easiest way to minimize time-delay skew is to match the physical lengths of the two lines. If one line starts out a different length due to its escape or fan-out from a BGA-via field, for example, you should make the other line longer as soon after the via field as possible. Unfortunately, time-delay skew can arise from causes other than length. The local speed of the signal due to local variation in the dielectric constant of the resin-glass composite can also affect time-delay skew.
Weave-induced skew occurs when one line sees a different dielectric constant from the other line due to proximity to a glass-fiber bundle. The impact of weave-induced skew is roughly 0 to 10 psec/in. and depends on the chance alignment of one signal trace adjacent to a glass bundle. A 20-in. trace on a board could see a weave-induced skew of 10 to 100 psec. When the entire unit interval for a 5-Gbps signal is only 200 psec, any skew larger than 20 psec eats up the total skew margin and begins to degrade the eye diagram (Figure 3).
The easy approach is to match lengths between lines that make up a differential pair so that the time-delay skew is less than a few percentage points of the unit interval. The more-involved problem is minimizing the weave-induced skew. Techniques for addressing this skew include rotating the routing axis from the glass-weave axis, adding a small jog in traces longer than a few inches so that the two lines mix the local dielectric constant, and using a glass that either is more uniform or has a dielectric constant closer to the resin.
Channel-to-channel crosstalk
The bit pattern in adjacent channels is uncorrelated. Any signal from one channel that couples over to an adjacent channel therefore acts as random noise, collapsing the eye, increasing the crossover widths, and introducing random jitter. Differential crosstalk in connectors, in via fields, and between differential pairs is typically –35 dB or less. When the received signal is –10 dB, the margin is usually adequate, and crosstalk is not a problem. However, far-end crosstalk between adjacent microstrip-surface pairs can easily exceed –20 dB. For example, in two edge-coupled, differential microstrips with 5-mil lines and 5-mil spacing, a 10-mil pair-to-pair spacing, a 40-psec rise time, and a 5-Gbps signal, the far-end differential noise is almost –10 dB for a length of only 10 in. Because far-end noise is so sensitive to rise time and coupled length, a simulation is an essential step in evaluating the impact of far-end noise in microstrip-differential channels (Figure 4). Even near-end noise in stripline pairs can pose a problem under some cases. When the signal at the receiver decreases as a result of 30 dB of loss and when you use 10 dB of pre-emphasis on the transmitter, you must reduce crosstalk to less than –50 dB to provide adequate margin. You usually implement this reduction by using low-noise connectors and increasing the pair-to-pair spacing in the backplane.
Successful design and implementation of robust, high-speed serial systems are tricky because interconnects are not transparent to the signal. Unless you take special care, one of the four signal-integrity problems—losses, discontinuities, skew, and crosstalk—can prevent acceptable performance. The first step is being aware of these problems. The second step is to identify their root causes and to develop design guidelines that enable navigation through the minefield. A software-simulation tool that can model signal-interconnect interaction and account for each of the four effects is an essential tool with which to gain confidence in a design before committing to hardware. The combination of best design practices, new materials, new technologies, and analysis tools can dramatically increase the number of successful high-speed-serial-link designs.
