Re-engineering obsolete ICs using FPGAs
This case study illustrates the design challenges and constraints encountered as FGPA design consultants at EmbeddedBlox re-engineered an obsolete low-power peripheral controller.
By Vipin Ahuja, EmbeddedBlox Inc. -- EDN, October 13, 2008
Product obsolescence is a fact of life in the IC marketplace. Given the rapid evolution of technology, and the relentless pressure for better, faster, cheaper parts, it is rare that the lifespan of an ASSP exceeds four years. For makers of short-lived consumer products or high-performance communications devices, a three to four year life cycle presents no issue. But, for those producing systems with a five to10 year life expectancy, such as industrial suppliers, product obsolescence is a critical issue.
Replacing an obsolete IC in an existing system is no easy task, though. Frequently, designing in an alternative application-specific standard product (ASSP) requires extensive system-level redesign, pulling resources from multiple disciplines such as hardware, firmware, software drivers and power engineering. For this reason, re-designing the obsolete part for a 1:1 replacement is often preferable. More often that not, however, the original system designers that specified and designed the system have moved on, and legacy design information may be scarce, at best. Packaging, supply voltage, power and other capabilities of current-day IC technology may not match those of the original part, as well. And, since standard ICs seldom differentiate or add significant value to a system, there is reluctance to expend significant engineering resources on a re-engineering effort.
For design teams facing the challenge of having to reverse-engineer a part, though, FPGAs offer a very attractive implementation option. With recent advances in FPGA technology, new low-power FPGA solutions have become very competitive with ASSPs and ASICs in terms of size and resources, power consumption, performance and price. FPGA-based chip solutions also offer design-specific customization and portability, as well as ease and flexibility of implementation that minimize design resources, design time, and design risk.
In 2007, FGPA design consultants at EmbeddedBlox re-engineered an obsolete standard product for industrial supplier, MetroTech. This design case helps illustrate how to address common challenges and efficiently implement a re-engineered solution.
Challenge: Replacing a low-power peripheral controller
In 2007, industrial supplier, MetroTech Corporation, was given an end-of-life notification for a peripheral control IC used in one of its battery-powered, handheld industrial products. The end product was not near its end of life, so MetroTech either needed to replace the expiring controller with an alternative ASSP device or re-create the original IC. Although redesigning the board using an alternative ASSP might seem easier from the hardware point of view, it could pose significant risks due to the necessary changes to the assembly language software code that had been qualified and proven over time. MetroTech determined that it would be quicker and easier to replace the original ASSP device with an FPGA-based solution and maintain the pre-existing firmware without any changes. By taking this approach, MetroTech could avoid re-designing the firmware, and also could eliminate the need for costly and time-consuming firmware and system testing and qualification.
The re-engineering effort was constrained by a number of factors. First, MetroTech's handheld, battery-operated device had a very low-power budget — less than 50mW at approximately 5Mhz. Second, no changes could be made to the legacy firmware, so the replacement had to be register-level and functional-level compatible with the system. Third, the board's 5V supply voltage had to be accommodated despite the fact that all currently available FPGA technology was compatible with a 3.3V supply or lower. And finally, the re-engineering effort would have as its basis only the firmware and original device datasheet from IC supplier, SGS Thomson Micro.
Primarily because of the need for register- and functional-level compatibility, MetroTech decided to employ FPGA technology to replicate the logic in the peripheral device. The company also elected to employ external engineering resources with expertise specific to FPGA technology and implementation for the redesign effort. Through the IEEE Consulting Services Network, MetroTech enlisted the design services of FPGA specialists at EmbeddedBlox for the re-engineering effort.
Meeting low-power constraints
Since the MetroTech product was battery-powered, power consumption was a key consideration. The device to be replaced was a low-power peripheral controller from SGS Thomson Micro (ST Micro), the ZPSD522B1, consuming, on average, 55mW (11mA @ 5V) on their current board. FPGAs typically do not offer power consumption comparable to application-specific or standard products, so determining whether an FPGA option existed that could meet the low-power requirement was an important first step.
Offerings from all major FPGA suppliers were evaluated using vendor-provided power estimating tools (See Table 1), and only the flash-based Actel ProASIC3 FPGA family was found to have power dissipation ratings within the desired range. Had additional power savings been required for sleep or standby states, the Actel IGLOO FPGA family might have been preferable. Since the ProASIC3 family met the requirements for this effort, though, and since the IGLOO family was just being released at the time, Actel ProASIC3 technology was chosen.
Addressing "instant on" requirement
Because most FPGAs are SRAM-based, a lag time of up to a few hundred milliseconds can occur upon power-up to load device configuration data from an external or internal PROM. This configuration data defines the logic inside the FPGA, so an SRAM-based FPGA device only begins to function like its ASSP equivalent once the data have loaded. In order to adjust for this lag time in the MetroTech design, changes would have been required to the system reset circuitry. Unfortunately, MetroTech would not allow any changes to the reset circuit, so it was necessary to select FPGA technology that would allow for "instant on" at power-up.
Fortunately, the flash-based Actel FPGAs also met the instant-on requirement. In Actel devices, configuration data is stored in flash cells, not in SRAM cells. Once programmed, they do not get erased when a device is powered down, so there is no lag time during subsequent power-up. Selecting flash-based FGPA technology was critical to the success of the project.
Achieving supply voltage compatibility
The MetroTech product had a 5V supply and required 5V TTL levels for I/Os, but available FPGA technology supported only 3.3V or below. For this reason, it was necessary to employ on-board voltage level translator buffers to interface between 5V and 3.3V I/Os. In addition, switching regulators were needed to accommodate the 3.3V FGPA interface and 1.5V required for the FGPA core itself. The regulators and translator buffers were implemented externally to the FPGA.
Reverse-engineering effort
As with any reverse-engineering effort, the task of recreating the ST Micro design was not straightforward. To reconstruct the design, EmbeddedBlox had only the firmware provided by MetroTech and the ST Micro datasheet. For EmbeddedBlox, having no prior knowledge of the firmware made it difficult to ascertain what was in the design based examination of the code alone. The data sheet provided more of the picture, but it lacked details about many aspects of the design that affected the functionality of the part and the way it interacted with the firmware. Specs in the datasheet, intended for the end user, focused primarily on connectivity and interface, not how individual blocks were designed.
In order to explore and reconstruct the design, the EmbeddedBlox team reverse-engineered the chip starting with the datasheet. The team gathered information from the datasheet, explored the firmware code, then took trace readings from a logic analyzer to observe sequences of interactions. By examining the output cycles, they were able to create a functional block diagram (See ), which was then realized in the FPGA implementation.
Implementation
The peripheral controller functionality was realized using an Actel A3P060-TQ144 FPGA with TI voltage translator buffers, 1Mb external Spansion Flash ROM and switch mode power regulators. The initial implementation for the replacement device (See 
) was a module that connected to the main system board via an adapter compatible with the original ST Micro ZPSD 68 PLCC (See 
). The six voltage translation buffers were placed external to, and surrounding the FPGA, and external ROM (See ) was needed to augment the ROM capacity of the FPGA. A block diagram of the adapter module is shown in 
. In order to reduce the size of the production implementation, MetroTech eventually re-spun the main board to integrate this functionality on board.
In order to minimize power consumption, logic in the FPGA was customized during implementation, taking care not to impact firmware compatibility. For example, the original ZPSD device contained four 16-bit programmable counter/timers. Since this application only uses two counter/timers, only two were implemented in the FPGA.
Configurability of the FPGA design was also maintained using modular design techniques so the device could be scaled as needed for alternative implementations. The actual re-engineered device contained all necessary logic to adequately replace the obsolete ST Micro chip (functions in solid box in ). The device could easily be expanded, though, to encompass any or all remaining functionality of the ST Micro device (functions in dashed box in ). Such expansion would likely require a pin-compatible higher density FPGA, such as the Actel ProASIC3 A3P125.
Mission accomplished
The resulting solution met or exceeded all design objectives. Under normal operation, the adapter module consumed 42.5mW (8.5mA @ 5V), compared to the ST Micro ZPSD511 device's 55mW (11mA @ 5V). The replacement device was fully compatible with the original firmware, so minimal re-qualification was required. The entire re-design cycle took only about three months, and no significant internal engineering resources were diverted by MetroTech since all the work was done by EmbeddedBlox. MetroTech, originally concerned that the re-engineering effort might not even be possible, was very pleased with the outcome.
Increasingly, industrial products require designers to re-engineer products due to product obsolescence. Seven to 10 years after introduction, end products more often than not utilize standard ICs that have become obsolete, forcing a redesign. Prior to the advent of FPGAs, this involved a significant re-engineering exercise, often involving resources from multiple disciplines, and many man-months of effort.
Re-engineering an obsolete device still involves its challenges, but FPGA technology significantly eases the task. Low-power FPGA devices, such as the Actel ProASIC3 and IGLOO products, make efficient and effective replacement of obsolete ASSP parts feasible for battery-operated and low-power applications, such as the product highlighted in this case study. With the growing variety and capacity of FPGA devices available today, an FGPA-based replacement is highly feasible for most IC replacement challenges.
