QorIQ moves Power architecture to multicore
By Robert Cravotta, Technical Editor -- EDN, June 16, 2008
Freescale’s QorIQ next-generation PowerQUICC (quad-integrated-communications-controller) processor line provides a migration path for embedded-multicore designs. The platform includes single-, dual-, and many-core devices that employ the e500 Power architecture. The first three of the planned five QorIQ processors families will be available for general sampling in 2009. Prices for the P1 and P2 products start at $23 and $50 (volume quantities), respectively.
The QorIQ P1 and P2 platforms comprise five package-, pin-, and software-compatible processors with single- or dual-core-processing options and operating from 400 to 800 MHz, targeting networking, telecom-line applications, and base-station-channel cards with thermal constraints. The QorIQ P1and P2 platforms include a 256- or 512-kbyte L2 cache that you can configure as SRAM or stashing memory. The integrated security engine supports security algorithms, such as IPSec (Internet Protocol security), Kasumi, and VPNs (virtual private networks). The memory controller supports both DDR2 and DDR3 memory and error-correcting codes. The integrated interfaces include SERDES (serializer/deserialzer), GbE (gigabit Ethernet), USB, and PCIe (peripheral-component interconnect express). The P1 series offers an encryption accelerator, and the P2 series integrates RapidIO.
The QorIQ P4 platform includes the P4080 multicore processor that integrates eight e500mc cores operating as fast as 1.5 GHz with a trilevel-cache hierarchy, CoreNet on-chip fabric, and datapath acceleration that supports active operation within a 30W maximum-power envelope. The cores can work as eight SMP (symmetric-multiprocessing) cores, eight AMP (asymmetric-multiprocessing) cores, or a combination of SMP and AMP groupings. Each processor can perform an independent boot and reset. The CoreNet fabric boosts performance by avoiding bus contention, bottlenecks, and latency issues associated with shared bus/shared-memory architectures. The datapath-acceleration architecture manages packet routing, security, QOS (quality of service), and deep-packet inspection. The QorIQ P4080 features dual XAUI (10-GbE-attachment-unit-interface) controllers, eight 1-Gbps GbE SGMII (serial-gigabit-media-independent-interface) controllers, three PCIe Version 2.0 controllers/ports operating as fast as 5 GHz, and two serial-RapidIO 1.2 controllers/ports operating as fast as 3.125 GHz.
The QorIQ P4080 has an embedded “hypervisor” that ensures that software running on any core can access only the resources that it is explicitly authorized to access. The hypervisor includes a peripheral-access-management unit, which provides address translation and access control for all bus masters in the system. Freescale has partnered with Virtutech to create a hybrid simulation environment that combines Virtutech’s Simics fast-functional model with a detailed performance model of the QorIQ P4080 processor. Before the emergence of first silicon, developers have a deterministic environment in which they can see and control everything without real-world-hardware constraints. A hybrid-simulation model of the QorIQ P4080 device is available now from Virtutech. Freescale expects the QorIQ P4080 processor to begin sampling in mid-2009.
