Magma takes on mixed-signal SoCs with Titan
Magma's Titan platform will provide an environment in which not-full-custom analog design can proceed in parallel with digital design, merging during the physical design back-end and working from a unified database.
By Ron Wilson, Executive Editor -- EDN, February 27, 2008
Driven in particular by consumer applications, SoCs have in recent years integrated more and more analog circuitry. The circuits in question have not been merely the unavoidable PLLs and high-speed I/Os, but also control loops and precision signal paths, the latter spanning both audio and video. This has forced SoC designers into the world of mixed-signal design.
To date there have been two main approaches to the mixed-signal SoC. One approach outsources the analog block designs, imports them again as hard IP, and hopes that they work. The other uses splendid specialist tool suites, such as Cadence’s Virtuoso, intended for skilled analog designers but integrated with digital flows. This allows analog experts on the SoC team to do a custom analog design in the same database the digital folks are using for the rest of the SoC design, somewhat easing integration and verification.
Today Magma Design Automation has introduced another alternative—one in keeping with the company’s guiding concept that modest designs shouldn’t require immodest expertise or license fees. The Titan platform will provide an environment in which not-full-custom analog design can proceed in parallel with digital design, merging during the physical design back-end and working from a unified database.
According to Magma vice president of product and business development Ashutosh Mauskar, Titan provides two paths by which a team can create analog designs. One is a schematic editor, from which the circuit description would be bound to foundry device models to create a simulatable netlist. The other is a rather unique IP-oriented scheme, in which Magma will define commonly used analog functions in terms of a topology template and a set of constraint equations. “The circuits will come right out of a textbook on analog design,” Mauskar said, “so they will be familiar and useful.”
Mauskar explained that this dual format—templates and equations—would allow Titan’s process migration tool to explore a range of alternative implementations in a new process technology within the constraint space, offering designers their choice of migrated circuit designs. Thus migrating an analog function in the Magma library to a new process node—while not exactly push-button—will be heavily automated.
Working in cooperation with the schematic and template tools, Titan will offer an analog simulation environment based on FineSim, and an analog placement tool. At this point the isolation of the analog and digital designs ends, and both the simulated and placed analog netlist and the digital Talus netlist flow into a merged tool suite.
That suite begins with a layout editor and a shape-based router. The latter, Mauskar said, understands analog-circuit constraints such as shielding styles and line length control, preserving the operating characteristics of at least conservatively drawn analog circuits through the routing process.
The final stage in the flow is an extraction, timing, and checking stage. For this Magma has incorporated its full-chip digital timing tools, LVS checking, DRC, and extraction. While these are familiar concepts for digital designs, doing a full-chip LVS or extraction for an SoC with analog blocks is a rather different matter.
Layout-versus-schematic checking for analog circuits, for instance, requires rules decks from both the user and their foundry, according to Mauskar. Extracting analog components and model parameters from shapes is not yet a solved problem, so the tools need this additional data.
And extraction, which can be based on some quite simple approximations for digital timing purposes, also becomes far more complex in the analog domain. Magma employs a new transistor-level extraction tool based on their well-regarded QuickCap capacitance extractor. Again, analog extraction is a work in progress, with future developments expected to lever the detailed extraction algorithms cell designers use.
All of the data for both the analog and digital nets goes into a unified database, which Mauskar said is Open-Access compliant. This of course reduces the version-control problems that can plague mixed-signal SoCs when the analog and digital designs proceed in isolation.
The Titan approach addresses a number of the problems with mixed-signal SoC flows. But it is not a panacea, a universal custom design tool, or a substitute for having skilled analog designers, Mauskar warns. The template-based approach to analog circuit design is more than adequate for normal, moderate-performance circuits, but it is not intended to push a process node to its physical limits, or to implement science projects. It is for moderate-performance functional blocks. Nor will the migration tool intervene in a circuit topology to find a better approach for that sigma-delta converter at 65 nm. It will just work with the existing topology and tell you what can be done. “The tools should work well with any technology node you can characterize accurately,” Mauskar said, “but there is no way to replace human intelligence on the most demanding requirements. That’s not what we are trying to do.”
This constraint probably becomes more important as designers use finer nodes, such as 65 and 45 nm, to implement critical analog signal paths. Most experienced designers at these nodes say that digital calibration and intervention in the analog design is necessary in order to get good performance. But the ability of a template-based approach, keeping the analog and digital simulation worlds somewhat separate until after placement, to cope with these tightly coupled mixed-signal designs remains to be seen.
Magma is phasing the roll-out of Titan over the course of the year. This quarter will see release of the Titan schematic capture, mixed-signal layout and routing, and chip finishing tools. The rest of the flow, the analog circuit templates and migration tool, and the mixed-signal floor-planning tool, will be released in beta form this quarter, and in production versions in Q3 of this year.
