Interfacing high-speed data converters

There are many ways to present a signal to a high-speed ADC. This article explains the tradeoffs between baluns, transformers and op amps.

By Hooman Hashemi, National Semiconductor -- EDN, April 18, 2008

ADCs (analog-to-digital converters) employ technology to sample and capture analog signals with high precision and at fast sampling rates. The complexity of data converters increases with high sampling rates and/or high number of bits. Data converters are specified with exact input conditions, which you have to adhere to in order to achieve the ultimate performance. It is a challenge to scale, drive, and interface the analog signal to the ADC input. This article will explore techniques to interface analog signals to high-speed data converters.

ADC input architectures and choice of driver

The analog-input configuration of an ADC varies depending on the number of bits of resolution and the maximum sample frequency. The input stage of the converter may be single-ended or differential. In addition, the inputs themselves may be high-impedance or they may be connected to switched-capacitor circuit elements. High-impedance inputs are sometimes called buffered inputs. Both of these factors influence the choice of the input driver.

Most ADCs pushing the limits of resolution and/or sampling rate are manufactured with differential inputs. Differential inputs offer advantages by lowering even-order harmonics and EMI emissions. Some differential-input ADCs allow you to use the device with a single-ended input by tying the unused input to the Common Mode (CM) reference pin from the ADC (Figure 1).

High-frequency analog input signals will degrade if you do not handle them properly. Such high-frequency applications benefit from low impedance (50Ω single-ended or 100Ω differential) analog inputs for the same reason most UHF and VHF circuits are 50Ω systems. For best distortion at high frequencies many ADCs have differential inputs. These devices usually do not offer the single ended/differential option. This is due to the tight specifications and the challenges of high-frequency, high-sampling-rate ADC operation. This class of ADC requires high-frequency, low-impedance input drive. To create high impedance input ADC's the chip designer buffers the analog inputs before sending the signals to the sample-and-hold (S/H) circuit for conversion. Thus, the normal decoupling circuit (series R, shunt C) employed in un-buffered ADCs is not needed. In the schematic of Figure 1, which uses an unbuffered input ADC, these decoupling components are shown as R1, R2 (18Ω) and C1 (25 pF).

Single-ended to differential conversion

An effective method of converting a single-ended input into a differential signal for use by the ADC is using a center-tapped transformer (Ruthroff transformer) as shown in Figure 1 (follow the "differential input" dashed lines to see how the transformer is tied to the ADC inputs). The differential input's common mode voltage (CM) should follow the VCOM voltage (output pin on the ADC) for proper operation of the sample-and-hold circuit within the ADC. The circuit in Figure 1 will allow setting the input CM by tying the transformer center tap to the VCOM output of the ADC, as shown.

The transformer's lower cutoff frequency will not allow the low-frequency content to be coupled in. Therefore, this type of coupling can only be employed in applications where DC and low-frequency content does not need to be acquired. In addition, this circuit suffers from high-frequency transformer-leakage effects, which limit its upper operating frequency and restrict its use to lower-speed applications. As can be seen from the insertion loss plot of Figure 2, a typical transformer has an upper and a lower frequency of operation. The low-frequency limit is dictated by the primary inductance. For this particular transformer, used with an 8-bit converter, the frequency range of operation is limited to a very narrow region within 1 to 100 MHz where the change in insertion loss is less than 0.034 dB (1 LSB), unless some other method of gain calibration or adjustment is implemented.

For maximum return loss (minimum reflection), many higher-speed applications require that the input impedance at J1 (input connector) in Figure 1 be controlled and that it matches the characteristic impedance of the cable tied to that connector. This is especially true if the length of this cable is longer than 1/20th the shortest wavelength encountered. As long as the transformer return loss does not degrade at the frequency extremes, it is possible to achieve this by placing a termination resistor, R_T, across the input. The input impedance will then be close to R_T, as the transformer return loss is large enough to have minimal loading effect. At higher frequencies, controlling the input termination gets more difficult with this type of transformer configuration because of the reduction in the transformer return loss. This is where a balun transformer offers several advantages.

Another approach to single-ended-differential conversion is with a balun transformer (Guanella Transformer), as shown in Figure 3. Looking into the balun, the 50Ω transmission line sees 50Ω to ground which provides proper termination. Compared to the scheme shown in Figure 1, this approach has the following advantages/disadvantages:

Balun transformer advantages:

1. Higher operating frequency.

2. Higher return-loss for broadband applications.

3. Better gain and phase balance.

Balun transformer dsadvantages:

1. More difficult to set the common mode (CM) voltage.

2. Inability to independently set gain and input impedance.

The balun configuration has a higher frequency of operation, compared to the center-tapped or Ruthroff transformer connection of Figure 1. However, with the balun, the ADC inputs must be ac coupled because of the inability in setting the CM (common mode) level. Some ADC's, will automatically bias their inputs to the proper CM value through internal resistors, if they are operated in the ac-coupled mode. A particular ADC that operates in the ac coupled mode if the ADC VCMO output is grounded is shown in Figure 4.

With the ac coupled arrangement shown in Figure 3 and Figure 4, the input coupling circuit's lower −3-dB frequency is 1/(2πR_eqC_eq) where R_eq=133Ω and C_eq= C_couple /2. The 133Ω equivalent resistance is the series combination of the differential load to the right of the coupling capacitors (which is the ADC's 100Ω input impedance) and the equivalent differential impedance looking into the coupling capacitors (R_T2 || 50Ω=33.3Ω).

With the circuit of Figure 3, J1 is terminated in close to 50Ω, assuming the ADC that is being driven has 100Ω differential input termination. This input impedance is maintained up to the frequency where the balun behaves as a transformer. Beyond this frequency range, which depends on the particular balun and its core characteristics, inter-winding capacitance, and other factors, the input impedance deviates from this value, leading to reduced return loss due to input reflections. Most balun datasheets list the upper and the lower operating frequency along with the return loss data at several frequencies.

You can compare the input return loss of a center-tapped transformer (Minicircuits TC4-14) and a balun transformer (Minicircuits TC1-1-13M) (Figure 5). As can be seen from the Figure 5 plots, the center-tapped transformer return loss declines rapidly below 700 MHz and beyond 1.3 GHz whereas the balun has decent return loss (>10 dB) above a few MHz and does not start its decline until much further in frequency at about 2.6 GHz or so. This is an advantage of the balun configuration over the center-tapped transformer. Reduced return loss at the higher frequencies results in a mismatch condition leading to higher reflected energy, which shows up as unwanted harmonics in the captured signal and reduces the ENOB (effective number of bits) performance of the system.

Return Loss (RL) is related to the 2-port input impedance as shown in equation 1. 

(1)

So, for example, RL of 10 dB would correspond to an input impedance of 96Ω or 26Ω (depending on the sign of the quotient in equation 1). The reflected wave at the impedance discontinuity (J1 in Figure 3) will arrive here after another reflection from the source end, at R_s1 (assuming the source and the transmission line are not perfectly matched). The round trip time would be l /ν, where "l" is the cable length and n is the speed of light through the transmission line medium. Different frequency components, which comprise the input signal, arrive back at the discontinuity after encountering this round trip delay and add with the original incident wave, contributing to the resultant signal. For harmonics which the round trip delay (2 l/ν) l is a significant portion compared (1/10) to their period T, the resulting waveform will be distorted. Mathematically, this refers to harmonics for which "T" satisfies T &=(20 l/ν). The reason is that, for the shorter period harmonics, the incident and reflected waves will add in staggered formation (in time), which would cause the waveform to alter. Herein lays the reason for the reduction in ENOB because this altered waveform will have distortion terms that increase the THD (total harmonic distortion) and thereby result in lower ENOB.

In spite of the balun advantages discussed so far, this configuration cannot be used to provide any voltage gain as the primary and secondary will always have a 1 to 1 ratio in order to the balance-un-balanced function. As discussed, transformers can be used for the conversion, however they have major drawbacks in broadband applications and in that they can never include DC and low frequency in their operating frequency region. For this reason, semiconductor manufacturers have introduced active devices to perform this function in order to address some of the shortcomings of the transformer coupling schemes. Several manufacturers now have a portfolio of differential drivers, most of them intended for interface to differential input ADC's. Among these are: National Semiconductors, Analog Devices, Texas Instruments, and Linear Technology. The drivers cover a range of speed, noise performance, distortion level, common mode range, output power level, insertion gain, among other set of selection criteria. Among the characteristics that they all share is the ability to convert a single-ended input to a differential output with common mode control and they are usually intended for single-supply operation with input voltages which could extend below ground.

Read more In-Depth Technical Features

One such device is the National Semiconductor LMH6555, shown in Figure 6. The LMH6555 is specifically designed to drive the 100W differential input of the ADC shown with up to 0.8Vpp, and to present a constant 50W input impedance to the terminating cable (not shown in Figure 6) to achieve the highest return loss. Most differential drivers available in the market are also designed with this in mind. The driver's input impedance could be a fixed internal resistance or, alternatively, it could be an "equivalent input impedance" due to the action of the differential feedback loop and/ or the common mode feedback loop. In addition, the single-ended input impedance and the differential input impedance may not have the expected 1 to 2 ratio. For the LMH6555, for example, while the single ended input is 50Ω, the differential input impedance is 78Ω. For the Linear Technology LT1993-10, the 100Ω differential input changes to 85.9Ω when driven single ended. You can insert external resistances in series or shunt with the input to manipulate the input impedance, within some range.

The LMH6555 will span the frequency range from DC up to 1.2 GHz (−3-dB bandwidth limit of the LMH6555). Accurate output common mode voltage control is maintained by tying the VCMO of the ADC to the VCM_REF input of the LMH6555. With this scheme, the user can acquire the full signal spectrum while the common mode control is automatically maintained by the LMH6555. The buffer (LMV321) shown in Figure 6 is to boost the current out of the VCMO pin of the ADC so that there is adequate drive for the VCM_REF input. This buffer may or may not be needed, depending on the output current capability of the particular ADC. Most other commercially available drivers have a similar output common mode control scheme, though the adjustment range of each is different and is closely related to the range of voltages expected by the intended ADC, unless the expected application is ac coupled which eliminates the requirement of driver output common mode control for the ADC. For example, the LMH6555's output common range of 0.95V to 1.45V matches the expected range for the Big Gig family of National Semiconductor ADC's covering 500MSPS to 3GSPS rates, allowing for dc-coupled connection to the ADC. Analog Device's AD8352, which is meant to drive the AD9445 using ac coupling only, has an output common-mode range of 1.2V to 3.8V. However, the AD8352 is primarily used with ac-coupled input and output for performance optimization. Texas Instrument's THS4511 output common mode voltage range is ±0.5V around mid-rail (2.5V) which fits the intended application of dc coupled driving of TI's ADS5424, 14 bit, 105MSPS converter.

Some differential driver's datasheets include "S-parameter" data. From the LMH6555's "S-parameter" plot, shown in Figure 7, it can be seen that the return loss (RL, which is the absolute value of S11 in dB) is between 20-38 dB from DC up to 1 GHz. This number can be compared against the typical balun RL shown in Figure 5b, which ranges from 16-35 dB, to see the advantage of the LMH6555 for broadband applications, as summarized in Figure 8.

Analog Devices' 1-GHz AD8350-15 differential driver S11 is listed as 0.057&&/span>−87.5º, which is equivalent to −25 dB which is not as good as the LMH6555. The AD8350's S11 performance up to 500MHz (return loss=12.2 dB) is in fact worse that of the balun shown in Figure 5b. There is enough variation amongst the differential amplifiers themselves which require your more careful examination and scrutiny in order to pick the right components for the best performance.

The LMH6555's gain (differential output to single ended input) is fixed at 4.7V/V with the configuration shown in Figure 6 where R_s1=R_s2=50Ω. This gain includes the loading of the ADC (100Ω in this case) onto the driver's 50Ω outputs. For cases where the input signal is larger in amplitude, the LMH6555 insertion gain can be lowered by increasing the value of R_s2 and R_s1. These two resistors should always be equal in order to keep the input balance for low output offset. An example is shown in Figure 9 where the gain of the LMH6555, which is at the receiving end of a 50Ω cable, is reduced using Rx and Ry. By proper selection of these component values, the input impedance to the LMH6555 circuitry (at J1) is kept at 50Ω in order to maintain impedance matching. Note that the two LMH6555 inputs see an equivalent impedance of 64.5Ω to ground each with the component values shown in order to maintain low output offset voltage. The input/output swing relationship of the LMH6555 is shown in equation 2.

(2)

R_s is the equivalent resistance that each of the LMH6555 inputs sees to ground (assuming that they are equal to each other). Increasing R_s will reduce the gain. The ADC shown requires 0.8Vpp across its differential input. It is possible to use the LMH6555 in applications where the input is driven by a transmission line that needs to be terminated properly with insertion gain independently set for proper ADC full scale amplitude. Figure 9 is an example where the single-ended input is driven by a 50Ω transmission line that needs to see 50Ω to ground for proper termination. In this example, the series and shunt resistances, Rx and Ry, are chosen to present the proper cable termination (50Ω) and also to get 0.8Vpp across the ADC inputs. Note that the common mode input impedance of the LMH6555 is 50W.

Equation 3 and equation 4 are the governing expressions which need to be solved simultaneously in order to come up with the external component values in Figure 9.

(3)

(4)

One way to arrive at a simultaneous solution to the two equations above is to use a spreadsheet to solve for the two unknowns (Rx and Ry). Using "Goal seek" within the spreadsheet and with reasonable initial guesses for Rx and Ry, one could find the value of Rx which would satisfy the 2nd expression above and similarly for Ry and the 1st expression above. Repeating this procedure several times will generate the resistor values needed. R_s2 then needs to be set to be equal to the equivalent impedance of the driven input as in equation 5.

(5)

It is important to note that the LMH6555 will maintain its low noise (19nV output referred flat-band) irrespective of the R_s on its inputs. This is because the LMH6555's input architecture is dominated by its equivalent input noise voltage and is independent of the source resistance.

Many of the commercially available differential drivers are fixed gain (e.g. LMH6555, AD8352-20, AD8352-15, LT1933-10). However, there are other ones, which allow gain control. Examples of these are LMH6552, AD8352, and THS4511. As far as gain is concerned, some manufacturers may claim that their device's gain is independent of the load. This essentially means that the driver's output does not include any series resistance. When gain, output swing, and loading effects of differential drivers are compared, this output series resistance and the ADC's input resistance should be taken into account.

Most amplifier-ADC interface also requires the use of series resistance and shunt capacitance in order to improve the transient response due to charge switching on the input of the ADC. An example of this is shown in Figure 10 with THS4509 and the R-C network required to drive the ADS5424.

In the case of the LMH6555 and its interface to the Big Gig ADC family, the amplifier-ADC connection does not require this R-C network, as shown in Figure 6. The main reason for this is that, in this case, the LMH6555 driver has built-in series output resistances on each output to provide load isolation.

Another advantage of the LMH6555 over the transformer scheme is reduced Gain Balance Error. Figure 11 shows the LMH6555 balance plot vs. frequency. For comparison, Figure 12 shows the unbalance for a typical balun transformer. The information presented in Figure 11 and Figure 12 is in slightly different formats, but the results can be compared. The LMH6555 information shown in Figure 11 is depicted as the ratio of output common mode to the total swing vs. frequency and is represented in dB. So, for example, below 1.2 GHz, the LMH6555's gain imbalance of −40dB corresponds to equation 6 gain delta between the two outputs. This is an improvement over the specified balun gain imbalance of 0.55 dB over the same frequency range.

(6)

In terms of phase, Figure 11 and Figure 12 are directly comparable. The LMH6555's phase delta of 2° below 1.2 GHz from Figure 11 is comparable to that of the balun shown in Figure 12.

Gain and Phase balance errors affect the signal acquired by the ADC in two ways. One affect is common mode shift, the other is differential shift. The ADC shown in Figure 6 requires that the common mode voltage of the differential inputs to be very close (within ±50mV) to the VCMO reference output it generates. This is one consequence of its 1.9V operating supply voltage as this low supply voltage constricts the voltage headroom of the ADC internal circuitry. If this common mode operating condition is not maintained, the full-scale distortion performance of the ADC will suffer.

In addition to this common mode phenomenon, any gain and phase imbalance of the two ADC inputs will result in errors in the acquired signal. For example, a 100-MHz repetition rate square wave which is subjected to the balun transformer gain and phase imbalance of Figure 12 will have 1.5% error in its peak value (see the sidebar, "The effect of gain and phase imbalance on signal integrity (simulated)"). An 8-bit data acquisition has an LSB of 0.39% of full scale, and the balun imbalance is equivalent to 3.8 LSB. It is essential to keep the gain and phase imbalance to a minimum.

Single ended to differential conversion of signals for interface to high speed ADCs is a challenging and non-trivial task of data acquisition and should not be overlooked when the highest performance is needed. This article has examined some of the considerations and challenges of the input signal interface and has analyzed the different techniques that can be used to achieve this end. The new National Semiconductor LMH6555 and similar devices from other manufacturers were also introduced along with the benefits of applying such devices in demanding applications.

References

Balun Transformers Minicircuits RF transformers Schmitt, Ron, "Analyze transmission lines with (almost) no math," EDN, March 18, 1999.

The effect of gain and phase imbalance on signal integrity (simulated) In order to investigate the effect of gain and phase imbalance of a balun transformer (TC1-1-13M) on the ADC differential input, a 100MHz square wave was used as a test signal in a PSPICE simulation environment. The test signal was represented by its first 14 harmonics in a Fourier series and subjected to an ideal single-ended to differential conversion with no gain or phase imbalance. The resulting waveform is shown in Figure A in green. The balun typical gain and phase imbalance data (Figure 12) was then used to modify each harmonic to mimic the balun behavior during the process of single ended to differential conversion. The resulting waveform is shown in Figure A in Red. The ideal and the non-ideal (balun typical data) waveforms were then compared, as shown in Figure A with the markers placed at the peak of the swing and found to be 1.5% in error with respect to the full 2Vpp swing: Error (%)= [−1.1482- (−1.1784) ] . 100 / 2 = 1.5% The residual modulation in both traces in Figure A is the result of the finite number of harmonics (14) used in the simulation. The comparison between the ideal and non-ideal is not affected by this limit.