Virage Logic adds 65-nm Common Power Format low-power standard cell libraries to portfolio
The IP company reminds that Common Power Format is meant to help SoC designers shorten design time by addressing low-power requirements early in the development process.
By Ann Steffora Mutschler, Senior Editor -- EDN, April 17, 2008
To help allow designers to manage low-power design projects targeting applications in the mobile consumer market that require advanced power-lowering design techniques such as power shut-down, state retention and multiple voltage islands, Fremont, Calif.-based semiconductor IP company Virage Logic Corp today announced its Common Power Format (CPF)-enabled 65-nm standard cell logic libraries.
Virage said its 65-nm ultra low power (ULP) product includes CPF technology views that identify specialized cells available in the library to allow advanced power saving capabilities such as always-on cells, isolation cells, level shifter cells, power switch cells, and state retention cells to support a full range of advanced low-power techniques.
CPF is used for specifying power-saving techniques early in the design process, and to allow sharing and reuse of low-power intelligence throughout the design process. Also, CPF is mean to allow all design, verification, implementation, and technology-related power objectives to be captured early in the design process and to further allow for application of that data from RTL to GDSII for improved designer productivity.
Brani Buric, VP of product marketing and strategic foundry relationships for Virage said the company is seeing increasing demand for CPF support from customers that wish to minimize chip power consumption.
Virage said it has completed its first customer delivery of the 65-nm libraries and expects to expand CPF support to other advanced node libraries based on customer request throughout the year.
