AMD and IBM collaborate on strained silicon
By Jeff Berman, News Editor -- EDN, December 13, 2004
AMD and IBM said today they will begin using a strained-silicon transistor technology designed to augment processor performance and power efficiency. Both companies will begin using the technology on their 90-nm processor platforms during the first half of next year.
The technology, dubbed Dual Stress Liner (DSL), allows transistor speed to increase by 24 percent while running at the same power levels as those without DSL, the companies claim. A team of engineers from AMD, IBM, Sony, and Toshiba developed DSL, although IBM and AMD are the first to deploy the strained-silicon with SOI (silicon on insulator) technology.
"Pursuing strained silicon will help people wanting to go into higher frequency run at a faster operating speed," said Max Baron, principal analyst at In-Stat/MDR (a corporate relative of EDN's). Strained silicon allows designers to raise operating frequency without going to a smaller process-technology node, Baron added.
Higher frequency with strained silicon, Baron added, increases speed, which will, in turn, quicken the development of multicore processors—an area in which IBM, AMD, and Intel are all active.
"Multicore extracts more performance than just high-frequency single processors, because high frequency has temperature, heat, and power barriers," Baron said. Engineers creating designs for multicore technologies will be able to use the new technology with their present design tools and methodologies, he added.
"This achievement with AMD demonstrates that companies willing to share their expertise and skills can find new ways to overcome roadblocks and help lead the industry to the next generation of technology advancements," said Lisa Su, vice president of technology development and alliances, IBM Systems and Technology group, in a statement.
