New architecture delivers low noise and power
By Robert Cravotta -- EDN, November 25, 2004
Rolling out a new 16-bit architecture, Dallas Semiconductor touts its MAXQ2000 as the first microcontroller to implement the 16-bit MAXQ core. The 20-MHz MAXQ2000 consumes power at 5 mA with VDD of 2.5V at 25°C for typical operation. To reduce clock noise and maximize clock usage, the MAXQ architecture performs each instruction in one clock cycle without implementing an instruction pipeline, meaning that instruction fetching, decoding, and execution occur in the same clock, including program branch and return instructions. To reduce clock noise that may adversely affect sensitive analog circuits, the MAXQ core performs almost all digital functions on the positive edge of the system clock; this technique enables a noise-free falling-edge ideal for performing analog functions.
The MAXQ2000 targets industrial and medical applications that require an LCD controller. It integrates a 64-kbyte flash, a 2-kbyte SRAM, a 16×16-bit hardware multiplier, an SPI master/slave port, and a 128-segment LCD controller on a single chip. The LCD controller uses four common and 36 segment drivers; each segment pin can also provide general-purpose I/O, many of which support interrupt operation. The MAXQ2000 is available today in a 68-pin QFN starting at $2.95 (10,000). The evaluation kit includes an LCD daughter board; a JTAG-interface board; and a time-limited version of the IAR C compiler, debugger, and simulator.
Dallas Semiconductor, 1-408-737-7600, www.maxim-ic.com.
