Multicore trend continues at Fall Processor Forum
By Robert Cravotta -- EDN, October 7, 2004
The integration of multiple processors cores on a single IC was the prevalent theme at the In-Stat/MDR Fall Processor Forum (formerly, the Microprocessor Forum) this week in San Jose. A number of companies, including AMD, Broadcom, Freescale, PMC-Sierra, Sun, and Via, introduced or demonstrated new or updated homogeneous multicore processor architectures.
AMD demonstrated its first dual-core AMD64 Opteron device in an HP Proliant server. Broadcom introduced its next generation SiByte family of dual- and quad-core devices targeting 13 to 23W power consumption at 1-GHz operation and featuring a shared L2 cache and new memory bridge that handles remote memory requests and implements the ccNUMA protocol. Freescale introduced its first dual-core PowerPC processor that includes a 1-Mbyte, unified L2 cache with ECC, Altivec out-of-order transaction capability, and SMP support. PMC-Sierra introduced its next generation of 1.8-GHz, dual-core, 64-bit MIPS multiprocessors based on the E11k core with multiple high-speed I/O buses and interfaces that is due out in the second quarter of 2005. Sun disclosed that the dual-core UltraSparc IV+ will initially support 1.8-GHz operation and includes enhancements throughout the cache system and upgrades to the on-chip memory controller and Sun Fire Plane system interconnect. Via announced its plans to build a 64-bit architecture to support media applications; announced the C5J, a 2-GHz, 90-nm device that will be available for sampling in the fourth quarter of 2004; and demonstrated the dual-core C5Ps as well as a dual- and a quad-processor board.
Bernard Meyerson, vice president and chief technologist for IBM's systems and technology group, presented the keynote address, in which he stated that, although the predictable reduction in transistor dimensions has been the primary source of performance gains for the past four decades, this type of scaling is no longer adequate because the passive and total power consumption for these devices is rising dramatically faster than the performance gains. As a result, “scheduled innovation” is now the major component in future technology plans to gain performance or cost-savings and avoid dramatic increases in power density. Meyerson showed that using tensile silicon nitride to strain an underlying NFET in 90-nm technology improves electron mobility and yields a 15% performance improvement without scaling. He also stated that dual-gated CMOS structures are inventions that supplant scaling for future generations of CMOS. He also identified holistic design innovations such as multicore designs, virtualization at the chip and system levels, and massively parallel systems as approaches that will drive future generations of semiconductor-technology performance gains.
Microprocessor Report Editor in Chief Kevin Krewell highlighted the trends for multithreading and multicore for PC and server processors. Multithreading can hide latency operations, especially long latency memory accesses. He addressed the types of multithreading, including switch on stall, round-robin, and coarse- and fine-grain multithreading. Simultaneous multithreading shares available execution units among all of the active threads, but it requires more complicated control logic. Krewell attributed multicore designs as ways of providing improved power efficiency because they can avoid hyperdeep pipelines and the attendant extra control logic and high cache-miss penalties.
AMCC announced its first PowerPC I/O processor, the 440Spe, which offers three PCI Express and PCI-X interfaces, an enhanced DDR memory controller, and an XOR accelerator for functions such as parity generation and check functions for storage applications. ARM announced the Neon technology, a 64/128-bit-hybrid SIMD (single-instruction-multiple-data) architecture that ARM will implement as a tightly coupled engine within the ARM architecture to accelerate media-kernel libraries for audio, video, 3-D graphics, and speech processing. The goal of the technology is to support programmable data access and manipulation as part of the normal ARM instruction stream. Cavium introduced its Octeon network-services processor that implements a dual-issue, MIPS64 cnMIPS core that includes packet-processing in-core acceleration, and it provides multiprocessing support, including fully coherent data cache.
Clearspeed announced the CSX600 coprocessor that expands floating-point support to 64-bit IEEE 754 and delivers 50 GFLOPS peak and 25 GFLOPS sustained. The array of processor elements includes 96 VLIW (very-long-instruction-word) cores that each include multiple execution units, such as a floating adder and multiplier, a 16×16-bit fixed-point MAC (multiply/accumulate) unit, and integer ALU with a shifter, and a load/store unit. MIPS announced the MIPS DSP ASE, a DSP extension of the MIPS32 and MIPS64 integer pipeline that provides new instructions and architectural states to improve the performance of common “media”-signal-processing functions, including saturation, dot product, and bit-reverse with a less than 6% increase in die size. Renesas Technology announced first-quarter-2005 availability of the SH3707 that combines a SuperH core; a PowerVR MBX graphics core; Super-Hyway interconnect; and a dual-port, 64-bit DDR controller that can handle six channel requests. Transmeta presented the Efficeon and highlighted its effort for migrating the Efficeon-1 architecture to 90 nm, leading to the Efficeon second generation products.
Fall Processor Forum, www.mdronline.com/fpf04.
