You be the judge

EDN's 15th Annual Innovation Awards Program

By Staff -- EDN, January 20, 2005

EDN's editors have chosen this year's finalists from the scores of candidates in our annual Innovator and Innovation Program. Now, we're calling on you to help select the winners. Read the detailed descriptions below, and carefully consider the entries for the most innovative products and people of 2004. Then go to our Innovation Web Site, www.edn.com/innovation  to cast your votes. We will accept only one ballot per person. The deadline for voting is Feb 1, so vote today!

EDN also prides itself on the depth and quality of its technical articles, whether staff-written or from outside contributors. Take a look at our nominations for Best Contributed Article and vote for the one you feel was best among some fine choices.

Finally, to celebrate our 15th anniversary of honoring innovation, we will present a special "Best of 15 Years" award. You can read about these finalists below as well.

EDN is honoring the finalists and winners at a reception in San Francisco on March 7. Please join us. See www.edn.com/innovation for all the details.

EDN's 2004 Innovator/Innovation Program

INNOVATORS

JIM WILSON AND THE BLACKFIN PROCESSOR DESIGN TEAM, ANALOG DEVICES

The acronym “DSP” has evolved from representing the words “digital-signal processing” to “digital-signal processor,” and now it’s perhaps back to “digital-signal processing” again. Indeed, it’s hard to call the chips that Analog Devices has derived from the Blackfin work “digital-signal processors.” Instead, the individual chips leverage digital-signal and RISC-processing capabilities to serve specific applications; witness the Fusiv architecture for media gateways that is nominated for an Innovation Award. Indeed, everything from mobile handsets to set-top boxes to audio/video appliances require a precise mix of processor technology, specialized I/O, memory, and other functions. Moreover, these applications require ramping computational capability along with reasonable price and low power.

Jim Wilson and his team of ADI engineers were tasked with developing a processor that offers high performance, low power, and ease of use for multiple design applications. The team delivered Blackfin, basing it on the MSA (Micro Signal Architecture) jointly developed with Intel Corp. The design team, including Jim Potts, Rich Schubert, Chris Mayer, Colm Pendergrast, and Stewart Patterson used the MSA’s dual-core architecture to develop the Blackfin processor’s 32-bit RISC-like instruction set and dual 16-bit DSP functions. Moreover, the team integrated specialty functions, such as quad 8-bit video ALUs that make the processor suitable for media-processing applications. The resulting chip achieves performance of 756-MHz/1512 MMACs. Analog Devices, www.analog.com.

ASHRAF LOTFI, JIAN TAN, TRIFON LIAKOPOULOS, ROBERT FILAS, ENPIRION

Power is becoming an increasingly difficult problem in system design as chips get more powerful and power-hungry and end products get smaller and smaller. Enpirion claims that power management consumes as much as 80% of the board area in a typical application, and that product size and features are constrained by the vast amount of power devices required. Enpirion’s team of President and Chief Technology Officer Ashraf Lotfi, PhD, Director of Semiconductor Technology Jian Tan, Director of MEMS Technology Trifon Liakopoulos, and Chief Scientist Robert Filas sought to address the power-supply-footprint problem by integrating an entire dc/dc converter on a chip. Indeed, the team started its work as the Power Technologies Research Group at Bell Laboratories. The result is the 3A/10W synchronous-buck dc/dc converter nominated for an Innovation Award.

Lotfi’s team achieved two breakthrough innovations that warrant recognition. The first is the development of high-power, high-speed MOSFET transistors that are compatible with low-cost CMOS-silicon-fabrication lines. These power MOSFETs can switch at speeds 10 times that of many devices and still maintain high efficiency. The high switching speed enables low-cost and small-footprint power topologies. A high-frequency MEMS (microelectrical-mechanical) inductor is the second critical innovation. Together with the MOSFET transistors, the MEMS magnetics, based on an iron-cobalt alloy core, enable the integration of the entire dc/dc converter into a single IC package. Enpirion, www.enpirion.com.

SUSANNE PAUL, SILICON LABORATORIES

It’s perhaps ironic that the DSPs and RISC processor that power today’s mobile handsets are often viewed as an easier challenge than the power amplifier that drives the radio. But robust power amplifiers in the tiny footprints that handsets demand don’t enjoy the Moore’s Law benefits available to digital ICs. Like other predominantly analog circuits, power amplifiers aren’t easy fit into the CMOS processes favored for low-cost manufacturing. While working on her lawnmower, Susanne Paul, a design manager for Silicon Laboratories, mulled over the problem—namely, the challenge of overcoming the gate-oxide-breakdown problem in CMOS power amplifiers.

Although the lawnmower provided no mechanical analogy that sparked her idea, the solitude spurred thoughts of an entirely new architecture that would work within the constraints of CMOS to design Silicon Laboratories’ CMOS GSM/GPRS power amplifier. By thinking beyond traditional ideas, Paul implemented a circuit approach rather than a device-physics approach, allowing innovation at the circuit level using standard process technology. Paul discovered a novel way of distributing the high voltages generated during amplification among multiple devices. Using this new architecture, no single device is subjected to any voltage greater than the gate oxide can tolerate. Paul also embarked on integrating all of the discrete components and passive elements into one monolithic IC. The typical software used to design ICs does not properly model these passive elements. So, Paul not only developed a new architecture, but also her own methods of modeling the circuit. The result is the Si4300 power amplifier, which is nominated for an Innovation Award. Silicon Laboratories, www.silabs.com.

ANALOG ICs

AD8318 1-MHz TO 8-GHz LOGARITHMIC DETECTOR/CONTROLLER

Historically, the bandwidth of wide-dynamic-range logarithmic amplifier ICs has been limited to about 3 GHz. Interstage mismatches and thermal drifts further limit logarithmic conformance accuracy. Additionally, increasing bandwidths bring greater input-referred noise, which further limits the low end of the dynamic range.

Meanwhile, designers of wireless-infrastructure equipment seek greater measurement accuracy in cellular bands to optimize transmitter power, improve spectral efficiency, and reduce system cost. The AD8318 logarithmic detector addresses both accuracy and temperature-drift issues and alleviates the need for external temperature calibration and compensation circuits. An on-chip temperature sensor—the source for a proprietary temperature-compensation circuit—also provides a temperature-dependent voltage for off-chip use.

The 8318 provides a measurement bandwidth that extends to 8 GHz for LAN applications, including the WiMax infrastructure. It also features a less-than-13-nsec response time for radar and burst detection. The chip’s output stage can directly drive a 50Ω line. Analog Devices, www.analog.com.

XRT CLASS D AUDIO POWER AMPLIFIER

A proprietary audio processor and Class D-controller IC lie at the heart of the XRT—the only class-D amplifier to meet the stringent quality and performance requirements of THX’s highest performance rating, THX Ultra2. The amplifier module’s multi-input front-end sample-rate converter accepts as many as four simultaneous inputs, each potentially at a different data rate.

An intelligent power-supply control improves power efficiency and improves audio performance by providing greater signal headroom. Protection features respond to abnormal conditions and automatically restore normal operation following critical events that force a shutoff.

The Class D-amplifier controller dynamically adjusts the PWM switch timing to optimize the amplifier’s performance. The 1-kW amplifier module provides eight 125W Class D channels in a package the size of a paperback book and features extensive OEM programmability. Unweighted SNR is 114 dB, minimum; THD+N is typically less than 0.025% at 1W and less than 0.15% at 125W with all eight channels operating. D2Audio, www.d2audio.com.

LTC5100 VCSEL DRIVER

The LTC5100 is a 3.2-Gbps VCSEL (vertical-cavity surface-emitting-laser) driver that provides clear eye diagrams with a minimum of external components. Data inputs are ac-coupled, eliminating external capacitors, and the dc-coupled, 50Ω output stage drives the laser without coupling capacitors, ferrite beads, or external transistors. Additionally, the output stage isolates the high-speed signal from the power supply, reducing RFI. The resulting layout is smaller, simpler, and less prone to signal-integrity issues.

The VCSEL driver provides extensive monitoring and control features. An on-chip multiplexer and a 10-bit ADC measure the laser current and voltage and the monitor-diode current and temperature. Measurement data is available for feedback and statistical process control through the driver’s I²C serial interface. Integrated 10-bit DACs eliminate the need for external potentiometers. An internal controller provides first- and second-order temperature compensation and laser safety features. The LTC5100 provides 60-psec rise and fall times with 10-psec p-p deterministic jitter. Linear Technology, www.linear.com.

Si4300 CMOS POWER AMPLIFIER FOR GSM/GPRS

Silicon Laboratories fabricates the Si4300 monolithic power amplifier for GSM (Global System for Mobile communications) and GPRS (General Packet Radio Service) in standard CMOS. It integrates all of the functions between the transceiver and the antenna switch, including input and output matching, thermal- and load-mismatch protection, power control, and filtering. The monolithic amplifier avoids expensive fabrication processes, such as GaAs and LDMOS, and multichip module assembly, instead using a standard TSMC process. It fits into a 3.9×6.4-mm ceramic package, reducing board area by 70% and external component count by 90% compared with competing multichip modules.

The Si4300 avoids CMOS’ historic constraint in this application—the gate-oxide breakdown voltage in the face of large signal voltage swings in nonlinear amplifier architectures. A new architecture distributes the high signal voltages among multiple devices.

The amplifier can deliver 34.2 dBm (2.63W) at a power-amplifier efficiency of 50%, which compares favorably with industry norms—32.75 dBm for low-band GSM and 29.75 dBm for high-band DCS. Silicon Laboratories, www.silabs.com.

ASSPs/SOCs

BLACKFIN FUSIV MEDIA GATEWAY PLATFORM

The Blackfin Fusiv Platform comprises Fusiv SOCs (systems on chips) that combine IP (Internet protocol)-communications support, secure network processing, and voice processing. You can pair these SOCs with Blackfin processors for media processing. The platform targets media-gateway applications from consumer VoIP (voice-over-IP) gateways to multiline VoIP PBXs, to triple-play (voice, video, and data) media gateways. At launch, ADI revealed the Fusiv Vx 150 and 200 chips, which integrate functions such as Ethernet and ATM ports, PCI, and voice codecs. The 150 can handle two to six voice channels and primarily targets residential use; the 200 can handle eight voice channels and targets enterprise applications. As the demand for phone lines and channels increases, designers can pair a Blackfin processor with the Fusiv chips to address performance requirements. ADI is also relying on Blackfin’s media-processing capabilities, including quad 8-bit Video ALUs, to support digital-video gateways.

Design engineers working on system development often struggle with the large amount of effort spent on system integration, optimization, and testing. Much of the innovation in Blackfin Fusiv lies in the scalable software provided in the form of VoIP stacks, voice codecs, security software, and other code needed to meld the packet-processing capabilities of Fusiv with the media-processing capabilities of Blackfin. Blackfin Fusiv provides wire-speed secure transport and dynamic quality of service for small packets for next-generation multiservice convergence platforms. ADI claims that Blackfin Fusiv handles 31 times the bidirectional secure throughput performance of competing processors and offers twice the benchmarked price and performance of conventional DSPs. Analog Devices, www.analog.com.

AR5006X WLAN MIXED-SIGNAL SOC

Single-chip SOC (system-on-chip) implementations of complex functions generally lead to the lowest cost products in the electronics industry. But, for wireless products, the sensitive RF circuits of a radio generally have been incompatible with the digital baseband processor, and most design still segregate the two components. Now, however, for applications such as 802.11 wireless LANs, designers can turn to a single chip that can support 802.11a/b/g. In the AR5006X, Atheros managed to integrate the radio, the baseband processor, and the MAC (media-access controller) onto a single CMOS IC. Moreover, the radio design supports both the 2.4- and 5-GHz frequency bands. Placing the RF, analog and digital baseband, and MAC on the same silicon enables a high level of integration, eliminating as many as 24 discrete components.

Atheros claims that the all-CMOS design sacrifices nothing in the way of performance. According to the company, the frequency synthesizer has 10-dB-better close-in phase noise than any available competing product. The receiver detects input RF signals in the range of microvolts at the presence of hundreds of millivolts of digital interference. The overall receiver sensitivity is in line with previous two-chip products. Moreover, power dissipation is 50% less than previous-generation chip sets. The design also supports the IEEE 802.11i security standard, and the company’s XR (eXtended Range) technology, which eliminates dead spots. Atheros Communications, www.atheros.com.

c.LINK-270 MEDIA-DISTRIBUTION CHIP

Home entertainment and, for that matter, the representation of all media types, has gone digital. PVRs (personal video recorders) download video and store it on hard drives, and PCs store music along with home movies. Sharing this material would be nice but requires a solid, high-speed network that is easy to install and maintain. Moreover, proponents of technologies from 802.11 wireless LANs to power-line LANs have failed to offer a way to move rich data, such as high-definition video, around a home. Entropic Communications, however, claims that it can move such data over coaxial- cable plants.

Entropic’s technology taps into the 4 Gbps of usable bandwidth above the video band between 860 to 2000 MHz on coaxial cable, already installed in virtually all US homes. Moreover, the coaxial LAN works though splitters and the ad hoc state of such home cable. The c.Link-270 product comprises two ICs: an RF front-end and a baseband controller with an embedded MAC (media-access controller). The chip supports the Ethernet, MPEG Transport Stream, and IEEE-1394 protocols over the same coaxial wire. A c.Link-enabled home network supports as many as 10 simultaneous channels, each of which has a data capacity of 270 Mbps for multiple simultaneous HD/SD MPEG Transport Streams and Ethernet packets. Entropic is a founding member of MoCA (Multimedia Over Coax Alliance) and is pushing for its chip sets to be integrated into TVs and other entertainment devices. Entropic Communications, www.entropic-communications.com.

MSM6100 MOBILE-STATION MODEM

Convergence is turning mobile handsets into much more than phones, with companies seeking to add media players, GPS (global-positioning-system) functions, and PDA capability. Indeed, 3G (third-generation) phones will require subsystems such as graphics and audio, just as PCs do. Qualcomm’s MSM6100 chip set and system software target precisely that 3G scenario. For example, MSM6100 integrates stereo audio, an interface to high-resolution in-phone cameras, media-recorder and -player functions, 3-D graphics for gaming, and highly accurate location tracking.

For consumers, the MSM6100 design translates into handsets with fully integrated multimedia features, such as MPEG-4 video encoding/decoding, MP3 audio decoding, advanced digital-camera functions, JPEG encoding/decoding, a 2-D/3-D-graphics accelerator for advanced gaming applications, gpsOne position-location technology, a Bluetooth baseband processor for wireless connectivity to peripherals, and a CMX/MDDI synthesizer. The MSM6100 also allows direct interfacing with advanced color LCD and controllers and offers data rates to 307 kbps. Qualcomm achieved broad feature support without boosting chip count in a handset. The SOC (system on chip) integrates an ARM926EJ-S RISC core and two low-power, high-performance QDSP4000 DSP cores. Together, the processors eliminate the need for the multimedia companion processors normally required for camera, video-based applications, MP3 music files, and MIDI synthesizer/CMX functions. Qualcomm, www.qualcomm.com.

COMMUNICATIONS AND NETWORKING ICs

PRS 5G/20G SWITCH FABRIC

In many communication or network systems, a distributed architecture is the key to cost-effective equipment designs that can handle the traffic specific to an application. AMCC designed the PRS 5G (5-Gbps full-duplex aggregate bandwidth) and PRS 20G (20-Gbps full-duplex aggregate bandwidth) packet-routing switches for such distributed architectures, which allow the switch fabrics to pair with network processors with or without a dedicated centralized fabric. For example, multiple PRS 5G ICs, in a meshed configuration, provide 20-Gbps user bandwidth without incurring the cost of a centralized switch fabric. Furthermore, the PRS 5G boasts power consumption of less than 4.7W; leverages leading-edge, 13-micron technology; and features high-speed serial links at 3.2 Gbps.

Designers can also combine the PRS 5G and PRS 20G in mesh mode, delivering edge/aggregation systems, with 10-Gbps uplinks. The devices offer advanced flow control with support for four priority levels, as well as full-bandwidth multicast capabilities. During initialization, you can configure the PRS 5G or PRS 20G for use as a distributed switch fabric or to connect to a centralized switch fabric, such as AMCC’s PRS 80G. The architecture allows system designers to offer right-sized gear with an upgrade path to higher aggregate throughput. AMCC, www.amcc.com.

ACCELARRAY GIGAFRAME STRUCTURED ASIC

Communication and network gear provides an ideal target for emerging structured ASICs that bridge the gap between the fast time to market of FPGAs and the density, performance, and low power of custom ASICs. Fujitsu Microelectronics devised the AccelArray family to yield ASIC-like benefits with back-end design times of two to four weeks. The GigaFrame platform adds the I/O and memory features that are necessary in communications applications.

Fujitsu’s AccelArray Giga Platform incorporates as many as 24 channels of embedded SERDES (serializer/deserializer), operating at up to 3.125 Gbps with total aggregated bandwidth as high as 150 Gbps—fully duplexed. Giga Platform’s SERDES implementation supports multiple standards, such as XAUI, PCI Express, Serial Rapid I/O, and Fiber Channel. By using the serial-communications scheme, designers can replace 16 I/O pins with just two (differential pair) per SERDES channel. A structured-ASIC platform with 24 channels, instead of 384 I/O pins, requires only 48 pins. The platform also includes 3 Mbits of true dual-port SRAMs and a DDR-memory interface. Using Fujitsu’s Giga Platform version, customers can realize initial silicon in Fujitsu’s 0.11-micron process technology within six to eight weeks, compared with the six-month turnaround time typical for ASIC implementations. Fujitsu Microelectronics, www.fujitsu.com.

88P8344 SPI PACKET-EXCHANGE CHIP

A major challenge in any communication-system design, flow control can be key to overall system performance. As part of its flow-control family of parts, IDT developed the 88P8344 packet-exchange chip to address the needs of interfacing four slower SPI-3 (System Packet Interface-3) links to one, higher speed SPI-4 interface. The design aims to eliminate back pressure for aggregated 10-Gbps traffic. SPI-3 back pressure differs between ingress and egress. In one direction, a device polls the SPI-3 logical port to determine whether the target can store a data burst. In the reverse direction, a congested logical port means all SPI-3 transfers are stalled.

IDT engineers applied queuing theory to this problem and concluded that the responsiveness of adjacent devices was a greater problem than the delay in a round-robin scheduler defined by the SPI standard. A downstream device that responds slowly to back pressure generally requires a longer “skid” buffer to avoid loss of in-flight packets. In the IDT packet-exchange device, ingress data are stored by ingress “lockers” and transferred to an  (logical-identifier) memory segment associated with an egress logical port. A burst processor can transfer packet fragments or bursts of packets and may be driven directly by egress back pressure. Ingress back pressure is triggered per LID when a “free-segment” threshold is crossed, providing very fast back-pressure response yet tolerating slow external response. The IDT burst processor provides large buffers with configurable thresholds and can even disable back pressure. IDT, www.idt.com.

DIGITAL ICs

STRATIX II FPGA FAMILY

Altera has historically made comparatively minor enhancements to its FPGAs' LABs (logic-array blocks), which contain eight to 10 logic-element pairings of a four-input LUT (lookup table) and register. With Stratix II, however, the company takes a revolutionary approach. A Stratix II ALM (adaptive-logic module) offers a collection of logic functions: a three-input LUT ahead of two four-input LUTs, two registers, and two three-input adders. To help design software efficiently use the available FPGA resources, Altera has built the ALM in such a way that its triple-LUT structure can implement a diversity of functions. Altera also doubled the number of inputs to and outputs from each ALM over the LE (logic-element) predecessor. Eight ALMs combine to form each LAB. The initial $125 (25,000) EP2S60 contains 24,176 ALMs, 2.5 Mbits of SRAM, 144 18×18-bit multipliers, and 12 PLLs. The complete family of six Stratix II devices ranges from 6240 to 71,760 ALMs and contains as much as 9.3 Mbits of SRAM. Altera’s latest generation Version 4 Quartus II design software offers device support for all Stratix II family members, including HardCopy variants. Stratix II chips also support nonvolatile, 128-bit AES security for their links to external configuration memories, along with 1-Gbps differential source-synchronous signaling and dynamic-phase alignment. Altera, www.altera.com.

3DM (3-D MEMORY)

Matrix's 3DM (3-D Memory), now shipping in production volumes in Mattel's Juice Box personal video player, is the first commercial IC designed and manufactured in three dimensions. Fabricated on a 0.15-micron process, 3DM costs less than flash memory and is cost-competitive with or, at high densities, cheaper than mask ROM. Unlike mask ROM, though, 3DM is one-time user-programmable and therefore not burdened with mask ROM's ASIC-like custom mask sets, which result in undesirable eight- to 12-week lead times, NRE charges, and minimum-order quantities. The product family delivers 1- and 2-Mbyte/sec write and read speeds, respectively, and is currently available in a NAND flash-memory pinout-compatible TSOP (16-, 32-, and 64-Mbyte densities) or an MMC (MultiMediaCard; 16-, 32-, 64-, 128-, and 256-Mbyte densities). Base pricing for a 64-Mbyte MMC is $9 (1000). The primary market for Matrix 3DM is content publishing for mobile devices, such as handheld computers, mobile phones, portable audio and video players, advanced toys, and game consoles, in which it serves as a lower cost, smaller, lighter, and lower power alternative to, for example, the combination of a writable CD drive and a CD-R disc. Matrix Semiconductor, www.matrixsemi.com.

VIRTEX-4 FPGA FAMILY

The Virtex-4 moniker comprises the FX, LX, and SX product families. Xilinx bases all of the devices on the same stripe-based ASMBL (application-specific modular-block architecture) device-organization approach, and each device offers features and proportions that reflect various application needs. Virtex-4's ExtremeDSP slices implement full multiplier/accumulator structures; prior generation Virtex-II chips contained only hard-wired multipliers and required the use of slower and less silicon-efficient FPGA resources to implement the accumulation function. Virtex-4 chips also include differential internal clocking that operates as fast as 500 MHz, serializer/deserializer structures within each greater-than-1-GHz SelectIO buffer, and RocketIO transceivers that operate as fast as 11.1 GHz. Virtex-4 FX chips even include a Gigabit MAC (media-access controller). Xilinx is now shipping devices in the LX and SX families; FX chips will follow in early 2005. Xilinx’s ISE Version 6.3i design software supports all Virtex-4 proliferations. The Virtex-4 LX25 and SX25 will cost $39.99 and $59.99 (25,000), respectively, by the end of 2005. Xilinx, www.xilinx.com.

EDA

ALLEGRO PCB SI 630

This addition to the Allegro family supports the transmitter and receiver device modeling required to handle advanced techniques such as pre-emphasis and equalization with either behavioral macromodeling or transistor-level representations. Using either Spice or S-parameter format, engineers can also model vias, lossy and coupled transmission lines, connectors, and packages. The tool also supports channel-analysis simulation, which allows much greater throughput than normal simulation techniques. The new tool allows simulations with as many as 10 million bits of stimulus in hours instead of days with traditional Spice simulators. Cadence, www.cadence.com.

DELTAFX SOFTWARE

A platform-based design methodology allows designers to take advantage of the latest semiconductor-fabrication processes and minimize the technical and financial problems inherent with developing a nanometer design from scratch. This technique enhances design reuse and provides additional fuel to the growth of the IP (intellectual-property) market. Providing designers with a way to maintain their design methodology and improve the connection between algorithmic description and device fabrication significantly enhances productivity.

With DeltaFX, Catalytic has automated the path from algorithm specification to implementation by automating the conversion of DSP floating-point algorithms to fixed-point versions. The tool allows designers to use the MathWorks’ Matlab to develop algorithms for a DSP core or discrete component and then translate the algorithm into fixed-point representation, a previously manual process. Designers now have at their disposal fixed-point constructs in Matlab, a numerical analysis and visualization environment, and a simulation-acceleration engine for Matlab. Catalytic, www.catalyticinc.com.

JASPERGOLD VALIDATION AND VERIFICATION TOOLS

One problem facing designers in verifying the functional behavior of a design is the confusion that exists between validation and verification. Validation is the operation that ensures that designers have correctly interpreted the specification requirements during implementation, and verification is the function that ensures that the resulting hardware correctly implements the higher level design. Most industry effort has focused on improving verification, and validation tools are just now under development.

JasperGold is the first product to validate a design against high-level requirements, enabling designers to validate their interpretation of a specification as they proceed with the implementation of RTL blocks. High-level requirements describe end-to-end behavior (from inputs to outputs) that a design must always or never exhibit. They represent design intent and cover large portions of the design. The product employs formal-verification technology to exhaustively verify functional behavior, enabling the Provably Correct Design verification methodology. Jasper Design Automation, www.jasper-da.com.

WEBENCH ACTIVE-FILTER DESIGN SYSTEM

The Webench from National Semiconductor consolidates all the tools to design an active filter in one place, allowing designers to take advantage of virtually any available transfer function with just a few clicks on a Web site. The product supports a selection of filter types, including lowpass, highpass, bandpass, and bandstop. The user can choose from several filter approximations, including Chebyshev, Bessel, Butterworth, and many elliptical-transfer functions. Designers can conduct Spice simulations of the filter within the Webench tool and compare the results with the initial theoretical transfer function. The tool uses proprietary algorithms to perform optimized topology and component selection and offers project-management options, such as inventory updating and credit-card purchasing. National Semiconductor, www.national.com.

EMBEDDED SYSTEMS

SBC4495 EPIC SINGLE-BOARD COMPUTER

The SBC4495 from Micro/sys is a 486/586-based single board controller in the new 4.5×6.5-in. EPIC-standard footprint. The board includes a temperature-compensated data-acquisition system with eight channels of 14-bit ADCs with simultaneous reads and eight channels of 14-bit DACs. The onboard GPS (global positioning system) also provides timing that can synchronize the data acquisition of geographically distant systems to within 190 nsec, along with providing location and altitude. A built-in expansion slot is compatible with a wide selection of off-the-shelf CardBus products. In addition to PC-compatible features, such as SVGA and four serial ports, the new single-board computer also includes 100BaseT Ethernet support, 64 Mbytes of SDRAM, and a CompactFlash socket. The onboard STPC Atlas processor offers speeds as high as 133 MHz, an on-chip cache, 64-bit DRAM access, and hardware floating point. The basic SBC4495 starts at $495 in single quantity. Micro/sys Inc, www.embeddedsys.com.

MVME6100 SINGLE-BOARD COMPUTER

Motorola’s MVME6100 single-board computer employs a 2eSST (two-edge source-synchronous-transfer) protocol for significantly faster VMEbus data-transfer rates. Compared with VME64's typical 40-Mbyte/sec transfer rate, the MVME6100 moves data across the VMEbus at 320 Mbytes/sec. Using Tundra’s latest VMEbus-to-PCI-X bridge in 2eSST mode, the MVME6100 also preserves compatibility with more than 20 years’ worth of VMEbus-legacy products. Key features of the board include an MPC7457 1.3-GHz PowerPC processor, a 128-bit AltiVec coprocessor for vector processing, as much as 2 Gbytes of DDR ECC memory, two 64-bit PCI-X bus interfaces, and dual gigabit Ethernet interfaces. Initially, Motorola will support the MVME6100 with a VxWorks board-support package and a Linux-support package.The MVME6100 costs $3995. Motorola, Embedded Communications Computing Group, www.motorola.com/computer.

COMPACTRIO EMBEDDED SYSTEM

National Instruments extends its popular virtual-instrumentation software to the embedded market with the introduction of a ruggedized embedded control and acquisition system. The new CompactRIO system allows developers to define custom-measurement hardware circuitry using a reconfigurable FPGA and LabView graphical-development tools. CompactRIO features a real-time embedded processor, a four- or eight-slot chassis containing a user-programmable FPGA, and 15 hot-swappable industrial I/O modules. Targeting a variety of applications, such as machine control, data acquisition, signal analysis, and system characterization, the CompactRIO system promises to erase the steep FPGA learning curve. Measuring 7.07×3.47×3.47 in. and weighing 3.47 lb, the four-slot CompactRIO system withstands temperatures of –40 to +158°F, 50g shock, and hazardous environments. CompactRIO embedded systems start at $2495. National Instruments, www.ni.com/compactrio.

INTELLECTUAL PROPERTY

XPM NONVOLATILE MEMORY

Designers can use XPM nonvolatile memory as a replacement for external memory chips in high-density embedded memory applications for publishing games, movies, and other multimedia content, as well as for secure firmware storage in embedded microcontroller- and DSP-based systems. Engineers can use XPM modules for secure ID and data storage for smart cards, embedded parameters, encryption keys, analog trimming and calibration parameters, or unique configuration codes for embedded-memory repairs.

The XPM fuse-programmable technology uses 1.5 transistors per memory cell, is programmable with a low current by either an external or an internal voltage source, and offers read-access times of 40 to 70 nsec for a 1-Mbit, 0.18-micron process. Applications requiring more than one-time programming can use a multiple-sector approach. For example, engineers can divide an 8-kbit XPM module into eight sectors to allow for reprogramming of parameters in the field as conditions change with a small amount of additional die area for the control circuitry. Kilopass, www.kilopass.com.

MOBILIZE POWER-MANAGEMENT IP CORE

In nanometer designs, leakage becomes a significant and growing part of the overall power cost for SOCs (systems on chips). By reducing static leakage and providing a method of actively reducing dynamic-power requirements, designers of mobile and battery-powered devices can maintain high performance levels and reduce power consumption. Mobilize Power Management IP core actively addresses the power and leakage issues in nanometer designs. Mobilize provides an adaptive, dynamically configurable option for reducing both static and dynamic power in 130 nm and smaller SOC designs.

Designers using Mobilize can significantly reduce static leakage and dynamic-power consumption without specialty processes to implement the Mobilize core, and they can apply fine-grained control to individual power islands. Introduced for the 130-nm process, Mobilize is portable to both 90- and 65-nm processes and does not rely on a lower performance process version to achieve power savings. Virtual Silicon Technology, www.virtual-silicon.com.

PASSIVE COMPONENTS/SENSORS

MX1000 LASER OPTICAL MOUSE

Rather than an LED, the MX1000 incorporates a laser diode, resulting in a 20-times improvement in surface-tracking power. It can track on smooth, glossy, translucent, and glossy surfaces that are difficult for the LED versions, due to the coherent nature of its laser light and the resulting high-contrast images. The device is the first to use a laser. (Previous laser-diode-based designs were too large and costly.) And the overall system combines sophisticated optical design, image sensing, and DSP functions to compare the sequential images. Resolution is 800 counts/in., and the image-processing power handles 5.8 million pixels of surface information per second. Agilent, www.agilent.com.

A132x FAMILY LINEAR HALL-EFFECT SENSORS

Housed in an SOT23W package, A132x sensors use proprietary design and trimming techniques and postpackaging programming to achieve temperature-stable quiescent output voltage and repeatable room-temperature sensitivity. Output voltage is proportional to the applied magnetic filed, and quiescent voltage is one-half the supply rail. Internal compensation circuitry in the BiCMOS IC reduces the inherent sensitivity drift, and an internal amplifier minimizes noise and offset problems. To overcome residual offset voltage caused by overmolding and thermal stress, the device also uses a dynamic offset-cancellation technique along with a high-frequency internal clock. It thus yields bandwidth above 20 kHz, an order of magnitude greater than other devices. Allegro MicroSystems, www.allegromicro.com.

SISONIC MEMS-BASED SMT MICROPHONE

The SiSonic microphone not only uses standard semiconductor-manufacturing processes, but also incorporates an innovative packaging technique to provide advantages over common electret microphones. A solder connection between the microphone and the pc board provides an acoustic seal around the sound porthole. The free-floating diaphragm is immune to stress variations that impact acoustic performance. Integral filter capacitors provide 900- and 1800-MHz EMI protection. The design occupies 40% less pc-board space than other microphones and has no added height penalty on the top side of the board. Designers can automatically handle the SiSonic like other SMT (surface-mount-technology) components; it comes on tape-and-reel packaging and is compatible with pick-and-place assembly machines. Knowles Acoustics, www.knowlesacoustics.com.

POWER ICs

EN5330 SWITCH-MODE SYNCHRONOUS DC/DC-CONVERTER IC

The EN5330 switch-mode synchronous dc/dc converter integrates control functions, power transistors, gate-drive circuits, compensation networks, and magnetics in one IC package. The converter exploits high-speed, high-power transistors developed for fabrication in low-cost CMOS silicon processes, which allow a significant increase in switching frequency and maintain high efficiency. The fast switching rate also allows the converter to use smaller reactive components than controllers operating with slower clocks and enables a wide-bandwidth control loop that provides superior transient performance.

Contemporary power inductors demonstrate poor performance at high frequencies and are bulky. Conversely, the magnetic alloy in the EN5330’s MEMS (microelectrical-mechanical-systems) inductor exhibits high inductance and excellent high-frequency performance, and it is manufactured in a standard CMOS process. The EN5330 can deliver as much as 3A or 10W. A VID (voltage-identification) pin selects one of seven standard voltages in the range of 0.8 to 3.3V. A resistor divider enables a continuous set-point range from 0.8V to V_IN. Enpirion, www.enpirion.com.

IR2520D ADAPTIVE CFL-BALLAST IC

The IR2520D CFL (compact-fluorescent-lamp) ballast control IC adapts to changing supply voltage, frequency, and lamp conditions to increase lamp life and reliability. The ballast IC includes a ZVS (zero-voltage-switching) circuit that maintains soft switching, regardless of supply voltage, frequency, and lamp conditions. The 2520 also provides internal-crest-factor overcurrent protection and an integrated bootstrap diode.

IR2520D ballast designs are self-starting and protect against lamp nonstrike and open-filament failures without DIACs and freewheeling diodes or positive-temperature-coefficient preheat thermistors. The control IC operates as close as possible to the resonance frequency of the overdamped RCL output stage and maintains ZVS at the half-bridge to keep the output current in-phase with the half-bridge output voltage. This operating mode results in minimum-current switching, which minimizes switching losses. Closed-loop control of the operating point allows the ballast IC to correct for lamp tolerance and track variations in line voltage and lamp condition over time. International Rectifier, www.irf.com.

DS2711 LOOSE-CELL NiMH AND NiCd CHARGER

The DS2711 ensures the safe charge of loose-cell NiMH and NiCd batteries. Targeting one- or two-cell applications, the DS2711 electrically analyzes each cell and determines whether the battery is rechargeable. If it is, AA or AAA cells can go from depleted to full charge in as little as 30 minutes. These features allow OEMs to incorporate the charger in a variety of portable products without risking the consequences of inadvertently charging an alkaline cell.

The DS2711 charge cycle’s first step checks the battery temperature and voltage to ensure suitability for fast charge. The charger tests for chemistry type using impedance-and voltage-relaxation criteria. If it determines that the battery is nonrechargeable, it ends the charge cycle and notifies the user of the fault condition. On a successful test, it proceeds to charge until it reaches a cell voltage peak, the charge timer expires, or the battery temperature crosses a threshold. Maxim Integrated Products, www.maxim-ic.com.

POWER SUPPLIES

CAR1248 FRONT-END/RECTIFIER

The CAR1248 combines innovative design with simulation-modeling techniques developed in-house to achieve its high power density. The unit’s front-end stage uses a proprietary power-factor-correction circuit to ensure ZVS (zero-voltage switching), and the main topology—a full bridge with ZVS—was optimized through closed-loop computer modeling. In addition, by switching at 450 kHz, the CAR1248 can use a smaller output choke with very low core and copper losses. Cherokee International, www.cherokeellc.com.

Z-ONE DIGITAL INTERMEDIATE BUS ARCHITECTURE

The Z-One Digital IBA (Intermediate Bus Architecture) reduces power-system components, as well as development time, through its use of digital integration of board-level power management and conversion. Parameters such as output voltages, sequencing, and warning-signal limits are user-programmed through a graphical user interface, communicated through an I²C bus, and stored in a DPM (digital power manager). At system start-up, the information stored in the DPM initializes as many as 32 programmable Z-POL (Z-point-of-load) converters.

After system initialization, ongoing communications between the DPM, Z-POL converters, and host system support intelligent operation. In addition, the Z-One Intelligent-power Operating System facilitates programming, communications, and fault management. Power-One, www.power-one.com.

PROCESSORS

PENTIUM M PROCESSORS

Intel built the 735, 745, and 755 Intel Pentium M processors on its 90-nm strained-silicon manufacturing-process technology. The Pentium M microarchitecture targets mobile computing by featuring intelligent power distribution and a power-optimized logic design to extend battery life and focus system power where the processor needs it most. Pentium M processors use Micro FCPGA (flip-chip pin-grid-array) and FCBGA (flip-chip ball-grid-array) packaging technology to support the form factor and thermal power requirements for notebooks less than 1 in. thick. The processors support up to 2-GHz operation and include microarchitectural enhancements. The Enhanced Register Access Manager facilitates more efficient management of CPU registers, and the Enhanced Data Prefetcher offers more efficient speculation and loading of data into L2 cache. The processors integrate 2 Mbytes of power-optimized L2 cache to reduce memory-data latency. Intel, www.intel.com.

S5610 SOFTWARE-CONFIGURABLE PROCESSOR

The Stretch integrates an ISEF (instruction-set-extension fabric), a software-configurable datapath based on proprietary programmable logic, with an Xtensa processor core. The company couples the ISEF with the extended five-stage pipeline, rather than offering it as a separate component, so the processor can handle multicycle ISEF instructions. The 128-bit extension registers provide wide data access to memory and to feed the ISEF. Developers can scale the clock rates for the processor core and ISEF block to improve performance and power consumption. The Stretch C compiler can abstract application code into custom hardware instructions that execute in the ISEF. Even though it implements the custom instructions in programmable logic, developers create and use them in an entirely software context. Stretch, www.stretchinc.com.

XTENSA LX CONFIGURABLE PROCESSOR

Tensilica’s Xtensa LX configurable processor features FLIX (flexible-length instruction-extensions) technology to enable higher computational throughput; ports, queues, and a second 128-bit-wide load/store unit to support higher I/O bandwidth; and fine-grained clock gating to enable lower power operation. The FLIX technology enables developers to intermix instructions of 16, 24, or 32/64bits. By packing multiple operations into a 32- or 64-bit instruction word, FLIX eliminates the performance and code-size trade-offs of a fixed instruction length. Ports are arbitrarily wide direct connections between two Xtensa LX processors or RTL blocks. Queues operate as processor registers to transfer streaming data and can sustain data rates as high as one transfer every clock cycle. The fine-grained clock gating touches every functional element, including designer-created functions, to prevent portions of the logic that are not in use on a particular clock cycle from consuming power. Tensilica, www.tensilica.com.

TMS32064x DSP

To produce the 90-nm, 1-GHz TMS32064x DSP, Texas Instruments developed a low-k dielectric material to reduce capacitance and propagation delays within the device’s interconnect layers. The processor relies on new voltage threshold (V_T) transistors at 90 nm to reduce the power dissipation from its more than 64 million transistors. Nominal V_T transistors support performance in the critical path circuits, and high V_T transistors for lower active-performance circuits—such as on-chip SRAM—reduce leakage current. To execute complex VLIW (very-long-instruction-word) instructions in one clock cycle at 1 GHz, Texas Instruments engineers developed special clock trees and leveraged the 90-nm high-performance cell library with significant timing margins in the critical paths while transparently maintaining 100% code compatibility with previous C64x designs. The TMS32064x can support as many as 55 GSM (Global System for Mobile)/adaptive-multirate channels, or eight channels of real-time D1 (720×480-pixel) MPEG-2 video transrating. Texas Instruments, www.ti.com.

SOFTWARE

INTEGRITY PC RTOS

The Integrity PC RTOS from Green Hills Software enables developers to integrate into their high-security and high-reliability systems legacy software that executes under other operating systems. Integrity PC can partition a system into virtual instances, each of which can host its own operating system, including Linux, with its own memory-protected virtual-address space and guaranteed availability of processor bandwidth and memory resources. Integrity PC is an extension of the Integrity RTOS that allows guest operating systems and their applications to operate as Integrity user-mode applications. It also prohibits these guest operating systems and applications from circumventing the protections that the Integrity RTOS is enforcing. This enforcement extends to monitoring all I/O operations, including network communications. Integrity PC supports simultaneous use of system interfaces, including multiple instances of the same or different operating systems in different partitions. Green Hills Software, www.ghs.com.

AUTOMOTIVE GRADE LINUX

Metrowerks’ Automotive Grade Linux makes the Linux operating system viable for the telematics market by meeting the automotive industry’s requirements for fast boot time, determinism, and power consumption. The technology supports a less-than-40-msec response time for in-vehicle bus communication and has been optimized for low power consumption on the Freescale Total5200 development platform. Metrowerks, www.metrowerks.com.

LOW-POWER DESIGN TOOL SUITE

Texas Instruments’ Low-Power Design tool suite enables developers to better plan, implement, and determine the power consumption of an embedded design. The tools can provide detailed power-consumption information earlier in the design cycle when major changes and trade-off decisions are easier to make. The tool suite includes the power-planning tools, which help developers explore alternate processor configurations to determine the net power consumption based on dynamic power-management techniques as well as memory and peripheral combinations. The Power Manager provides services within the DSP/BIOS real-time kernel for automatic management of clock domains and sleep states. The Power Scaling Library simplifies processor configuration and scales the system voltage and frequency. Texas Instruments, www.ti.com.

TEST AND MEASUREMENT

B4655A FPGA PROBE

In the past, changing the probe points for a complex FPGA consumed hours of time, because engineers had to recompile the FPGA to select a new group of internal signals. Designers can now perform the same task in seconds using the Agilent FPGA dynamic probe, allowing design teams to more quickly validate their Xilinx FPGA designs. Traditional logic-analyzer probes limit engineers to measuring signals at the periphery of the FPGA; the FPGA Dynamic Probe allows engineers to measure as many as 64 internal FPGA signals for each debugging pin and quickly identify design problems. In addition, the probe can map internal signal names from the FPGA-design tool to the logic analyzer. The signal-naming capability of the FPGA probe reduces mistakes and the time needed to manually set up signal names, bus names, and logic-analyzer connections. Agilent, www.agilent.com.

BERTSCOPE 12500A BER ANALYZER

The BERTScope 12500A BER (bit-error-rate) analyzer combines the eye-diagram-analysis capabilities of high-bandwidth sampling oscilloscopes together with BER-pattern generation and analysis. Sample-rich eye diagrams originate from the same multigigabit-per-second sampling capability as the BER-detection circuit, providing far more complete characterization of waveform variations than existing digital communications analyzers, which are limited to sampling rates below 250k samples/sec. The BERTScope’s eye diagrams give a view of sampled data that directly correlates to BER measurements, enabling engineers to determine which specific bit and pattern sequence is responsible for an eye-diagram mask violation, worst-case jitter, or slowest rise time. SyntheSys Research, www.synthesysresearch.com.

TDS5000B SERIES DPO OSCILLOSCOPES WITH MYSCOPE

The TDS5000B series oscilloscopes provide insight into signal behavior by displaying, storing, and analyzing complex signals in real time, so engineers can more efficiently design, debug, and test devices. The TDS5000B Series incorporates MyScope, a new capability that enables engineers to quickly and easily customize the oscilloscope's user interface to meet their unique requirements. Oscilloscopes are expanding, both in terms of performance capabilities (including bandwidth, sample rate, record length, and waveform-capture rate), as well as in new features and analysis packages. Added capabilities, however, add complexity for novice and powers users alike. In a shared oscilloscope environment, each user can create his own MyScope control windows, tailoring the user interface to his exact needs without impacting his coworkers’ test setups. In fact, each user can have many unique control windows for different tasks. Numerous context-sensitive right-click menus further increase efficiencies by providing a shortcut to the actions or features relative to those special objects. Tektronix, www.tek.com.

BEST CONTRIBUTED ARTICLES OF 2004

• Design-planning guidelines prevent chip surprises, by Steve Lloyd, Rick Mitchell, Ron Spillman, Jonathan Young, Synopsys Professional Services, Feb 5, 2004.

• A universal approach to hot-swapping power in telecom systems, by Bob Neidorff, Texas Instruments High Performance Analog Products, March 4, 2004.

• Simple circuitry for cellular-telephone/camera-flash illumination, by Jim Williams and Albert Wu, Linear Technology Corp, May 27, 2004.

• Analysis of board layout helps cure jitter problems, by Eric Bogatin, PhD, Synergetix, and Gene Garat, Mentor Graphics, Aug 5, 2004.

• Safety isolation protects users and electronic instruments, by David Lohbeck, National Instruments, Sept 30, 2004.

• Choosing the perfect TFT display (Part 1 and Part 2), by Rob Dautel, All American Semiconductor, Feb 5, 2004 and Feb 19, 2004

BEST OF 15 YEARS

1996: COOLRUNNER CPLDs, PHILIPS SEMICONDUCTOR/XILINX

CoolRunner marked the time when programmable logic became sufficiently dense and fast enough to do some “heavy lifting” in designs. Moreover, features of that architecture led to the incredible FPGAs we have today. Philips designed these CPLDs, although Xilinx later bought this business from Phillips. Longevity is a key in any all-time innovation choice, and the CoolRunner continues today to be a leading-edge product for Xilinx. The 1996 write-up follows:

There are two key technologies in CoolRunner that give you fast, high-density CPLD (complex-PLD) chips: XPLA (extended-PLA) architecture and Philips’ FZP (Fast Zero Power) design technique. XPLA combines PLDs and PALs on one device, providing the advantages of both types of logic. You use the PAL to provide the highest speed when you can implement a logic function within the PAL array’s five dedicated (PTs) product terms. You employ the PLA for logic functions needing more PTs, using PT sharing instead of PT steering. PT sharing lets multiple macrocells share a PT. The maximum incremental delay with a CoolRunner chip is 2.5 nsec, whether a design uses one or all of the 32 available PTs in a PLA array. XPLA-based CoolRunner devices thus give increased logic capacity and higher speed than do CPLDs that use a traditional PLA architecture.

FZP design replaces the sense amplifiers, which reduce capacitive loading in long word lines, with a chain of CMOS gates. This technique eliminates the static current that each sense amplifier/PT requires, and it reduces standby current in any CoolRunner device to less than 100 μA. CoolRunner chips also offer significantly lower dynamic power, set by gate switching times. The advantage of a reduced-power CPLD structure is a CPLD family with high-gate-count chips. Philips has developed both 5 and 3V CoolRunner devices, with prices starting at $18.47 (100).

2000: C55x FIXED-POINT DSP, TEXAS INSTRUMENTS

This nomination as an all-time innovation finalist is about both the C55x and the legacy of family members that goes back to the TMS320C50 family of fixed-point DSPs that were first a finalist 1990. (In those days, most people didn’t know what a DSP was, and EDN didn’t have a DSP or even a processor category separate from other ICs.) The C50 family has been incredibly successful in products ranging from modems to digital media players to mobile handsets. The write-up from 2000 follows:

The C55x low-power, high-performance DSP employs parallelism and focuses on power dissipation. This fixed-point device combines selective enabling/disabling of six functional units with an automatic turn-on/turn-off mechanism (transparent to the user) for peripherals and on-chip memory. A 32-bit program reduces the number of internal and external fetches by minimizing memory accesses, and a cache with burst-fill minimizes off-chip accesses. Increased parallelism and double actions per cycle minimize cycle counts per task, and the device can turn off its multiplier unit when its simpler arithmetic unit can perform desired math operations. Although it is compatible at the assembly-language level with the C54x code base, the compiled code for this DSP is 30% smaller per function for control code and also yields a fivefold improvement in performance over the C54x at one-sixth the power.

1992: PENTIUM PROCESSOR, INTEL

The Pentium Innovation win came amid a three-year Intel winning streak—486, Pentium, and Pentium Pro. Intel was delivering both the processor technology that let the company build the Pentium and the architecture that allowed CISC to catch up with the hot RISC processors of the day in performance. The 1992 write-up follows:

Intel’s Pentium processor combines RISC technology and a CISC instruction set to deliver second-generation RISC performance. Running with a 66-MHz clock, the chip’s integer performance is 64.5 SPECint93, and its floating-point performance is 56.9 SPECfp93. It achieves this performance using a RISC-instruction-first implementation and a redesigned X86 floating-point architecture.

Unlike the 486, Pentium is a superscalar implementation: it has two four-stage execution pipelines, each with its own ALU. Pentium can issue two instructions for execution on each clock. The instructions are fetched and decoded in a common stage and then dispatched to the pipelines. To speed execution, the fetch stage plucks out one 256-bit cache line at a time to ease decoding of two instructions simultaneously. The wide instruction buffer and a two-stage decoding process help to minimize the difficulty of decoding and executing the X86’s complex, variable-length instructions. Additionally, the Pentium has a redesigned FPU with individual addition-, division-, and multiplication- execution units, as well as its own register file.

The logic decodes and executes RISC-like, simple instructions as a primary objective. The chip’s on-chip memory comprises two 8-kbyte caches, instead of the 486’s single 8-kbyte unified cache. It also has a branch-target buffer, which holds branch-target address information to speed branches. To keep the pipelines fed, the external bus is 64 bits with four double-word burst pipelines. The processor comes in a 273-pin PGA and costs less than $1000 in early production.

1990: HP54600A 100-MHz DSO, HEWLETT-PACKARD/AGILENT

Digital-storage oscilloscopes fundamentally changed the way design engineers debugged circuits, and the HP54600 scope was the fist of many such scopes to win an Innovation Award. Agilent still sells the 54600 family, which now includes members with bandwidth specifications as fast as 500 MHz. Moreover, the classic user interface, compact portable package, and reasonable price have kept this product family popular for more than a decade. The 1990 write-up follows:

The $2395, two-channel HP54600A and $2895, four-channel HP54601A DSOs (digital-storage oscilloscopes) couple analog-style controls—separate knobs for such functions as gain, position, and sweep speed—with real-time performance. No perceptible lag occurs when you observe the output of a circuit under test and manually adjust the parameters of that circuit. With the exception of a few expensive scopes that incorporate high-speed DSP microprocessors, nearly all DSOs exhibit a noticeable lag in display updates.

The scopes have an analog bandwidth of 100 MHz. You can use the entire bandwidth when viewing repetitive waveforms. The scopes have a resolution of 8 bits and a maximum vertical sensitivity of 2 mV/div.

1991: ADXL50 ACCELERATION SENSOR, ANALOG DEVICES

Acceleration sensing has become important in everything from cool X-Box joysticks to air bags for cars. Who knew the significance of this single-axis sensor in 1991, but the products spawned a successful family of products for Analog Devices, including its MEMS program. In fact, the company in 1988 won a second Innovation award with the two-axis ADXL202 2-axis sensor. The 1991 write-up follows:

The ADXL50 acceleration sensor combines a surface-micromachined capacitive sensor with on-chip signal-conditioning and self-test circuitry. The sensor can gauge collisions, judge inertial positioning, and monitor active systems. Its primary application is automotive air-bag systems.

Surface micromachining is a process for making silicon structures that can move. Multiple thin films—as well as layers of silicon and silicon oxide—are deposited and etched to produce movable parts with dimensions of 1 to 2 mm. This process lets electronic circuitry and micromachined structures reside on the same chip.

The ADXL50 measures acceleration in a single plane of sensitivity over the 650g range to an accuracy of 5%. Unlike accelerometers that monitor the resistance changes of stressed piezoresistors to detect acceleration, the ADXL50 measures changes in capacitance and is therefore insensitive to temperature changes.

The signal-conditioning circuitry provides excitation signals for the sensor and amplifies the analog output signal. The ADXL50 comes in a 10-lead TO-100 can and costs $23 (100). The sensor is also available in other package styles, and it costs $5 in automotive OEM quantities.

1991: DSP STATION SOFTWARE, MENTOR GRAPHICS

As with all of the Innovation categories, choosing a single EDA candidate for the “best of 15” was difficult, especially with candidates such as synthesis and verification tools that make today’s ICs possible. The DSP Station, however, was an uncanny offering in its day, given the fact that no one then was predicting that DSP technology would be the key enabler behind mobile phones, media players, digital cameras, and other hot products. Moreover, the product addressed designers’ needs, whether the target was off-the-shelf processors or full-custom ASICs. The 1991 write-up follows:

The DSP Station software performs top-down design of DSP systems from high-level specifications through simulation and optimization from multiple physical implementations. The software provides analysis tools that address the needs of DSP designers, such as noise and stability analysis, area versus bandwidth trade-offs, and frequency-domain sensitivity analysis.

DSP Station also helps you plan development and production times for your proposed DSP system and analyze cost/performance ratios. For fast implementation, you can use the software to generate assembly code for a commercial DSP chip. For quick prototype development, you can synthesize a design for a gate array or an FPGA. For the best cost/performance ratio, you can use high-level synthesis to create designs for standard-cell-module generators. DSP Station lets you use a common input format to drive all the implementation paths.

The software also helps you analyze hardware/software trade-offs, as well as analog/digital partitioning, from the early phases of design. It also lets you compare various system architectures.

The package includes three forms of synthesis: filter designs, assembly-language code for programmable DSPs, and DSP architectures for custom ICs.

The filter-design synthesis uses arithmetic optimization techniques in addition to the normal filter approximation routines. Assembly-language synthesis uses optimizing techniques to map all your DSP functions onto the architecture of the target programmable processor. Silicon synthesis uses either bit-serial or -parallel modules configured in an optimal design based on scheduling for each signal-processing task.

The product, with prices starting at $33,000, represents a cooperative development effort of a university research lab (Interuniversity Microelectronics Center), an industrial customer (Philips), and a commercial CAE vendor (Mentor Graphics Corp).