Memory manifests mass-storage muscle
By Brian Dipert -- EDN, October 28, 2004
Semiconductor memories, with their dense, repeatable array structures, provide perhaps the paramount illustration of Moore’s Law’s promise. Renesas’ 4-Gbit AG (assist-gate)-AND flash memory, the company’s first 90-nm-based device, is less impressive in this regard than its name might first imply, albeit still a significant achievement. The chip employs MLC (multilevel-cell) techniques to store 2 bits of information within each cell; this fact still means, though, that the device contains 2 trillion transistors in the memory array alone, plus additional peripheral circuitry. When Renesas moved from a conventional AND architecture to the AG approach in the 180-to-130-nm-process conversion, yielding its single-die, 1-Gbit and dual-die, 2-Gbit memories, the cell size decreased by two-thirds Converting from a 130-nm lithography to the 90-nm process, as part of the 1-to-4-Gbit transition, yields an additional 67% silicon-efficiency improvement.
Renesas’ 4-Gbit memory comes in an R1FV04G13R variant with an 8-bit data bus and an R1FV04G14R variant with a 16-bit interface; each sells for $55 (10,000). The R1FV04G13R is package- and pin-out-compatible with the company’s previous AND devices, although you need to update your software algorithms to reflect its different device identifiers, two-times-larger erase block, and consequent lower erase speeds. The company also claims that its AND devices are package-, pin-out-, and command-set-compatible with chips from NAND competitors such as Samsung and Toshiba. The R1FV04G13R and R1FV04G14R are available now in 3.3V versions that respectively deliver 10- and 12.5-Mbyte/sec sustained write speeds; the company also plans lower power, although slower, 1.8V variants for the first quarter of next year.
Renesas Technology, 1-408-382-7500, www.renesas.com.
