The November Euro-SOC Marathon: Is Europe taking the lead in SOC conferences?
One recurring theme: Know your development costs and the size of your product's market. Development costs can make or break your project.
Contributed to the EDN on EDA newsletter by Steven H. Leibson, Technology Evangelist, Tensilica -- EDN, December 11, 2003
Two very technical SOC-design conferences were held in Europe during November. These conferences delivered a double dose of information for SOC designers who are grappling with severe problems associated with designing mega-gate SOCs. The first conference, the fifth annual IP Based SOC Design Workshop (IP/SOC 2003), held in Grenoble, France was run by Gabriele Saucier’s Design and Reuse organization. The second conference, also in its fifth year, was the International Symposium on System-on-Chip 2003 (SoC 2003 for short) and was held in Tampere, Finland, which is adjacent to Nokia, both the town and the cell phone manufacturer. Processor Jari Nurmi of the Institute of Digital and Computer Systems at the Tampere University of Technology (TUT) organizes this SOC conference every year. Both conferences brought speakers and exhibitors from around the world to focus on today’s most significant SOC design issues.
IP/SOC 2003 brought in more than 300 attendees from around the world. It started with several keynote presentations from Dr. Santanu Dutta, IC Design Manager at Philips Semiconductors, Ted Vucurevich, CTO of Cadence, Dr. Raul Camposano, CTO of Synopsys. One of surprisingly consistent message from many of the IP/SOC 2003 keynote speakers was an emphasis on the growing design gap between Moore’s-Law transistor scaling, which now makes tens of millions of transistors available to chip designers, and the lagging rate of designer productivity improvement, which makes it increasingly difficult and costly for SOC design teams to leverage those millions of transistors.
Dr. Dutta’s kick-off keynote, "Recent Trends in Multi-Million-Gate SOC Designs," highlighted several key observations that were later echoed by other speakers. Dutta first pointed out that new products and services (such as advanced cellular phone services) drive the creation of standards (such as cellular video and multimedia messaging), which in turn drive the creation of new implementation algorithms. Because many of these standards are used across a number of related products and services, it’s possible to use the same hardware resources—an SOC design
for example—for multiple applications, thus reducing the need to design a new SOC for every new or upgraded product. Dutta calls the process of making one SOC design fit many applications "deverticalization," which is accomplished by making the SOC more flexible and programmable. Programmability, Dutta said, is also key to avoiding the absolute need to home in on the correct design with first-pass silicon: programmability allows design teams to tweak designs after the chip has been fabricated.
In a remarkably parallel presentation, Vuvurevich’s keynote speech, which immediately followed Dutta’s, echoed these observations and conclusions while adding some hard numbers to the equation. Vuvurevich said that combined hardware- and software-design costs for 90nm SOCs were now in the vicinity of $25M. He added that such SOCs must address markets in the range of $2.5B to justify such an investment in chip-development costs. The keys to financially successful SOC design lay in maximizing the TAM (total available market) over time and across product functionality, amortizing the risks and costs of the design, and optimizing the implementation. Vuvurevich also echoed Dutta’s conclusion about the need for programmable SOCs, but with his own twist. He said that the key to designing successful SOCs was through the creation of programmable, platform devices.
Synopsys’ Dr. Camposano had different numbers than Vuvurevich, but reached similar conclusions. Camposano said that 36% of SOCs designed in 2003 incorporated more than 4 million logic gates (excluding memory) and that the average chip design cost was now around $9.1 million. As a consequence of the increasing transistor count and the increasing design costs, Compasano predicted that IP block usage as a percentage of SOC gate count would grow from 50% in 2000, to 80% in 2005, and 95% in 2010 because "IP use is the only thing that scales." "Good IP design," said Compasano, "makes development time and performance predictable and makes the integration time linear with the number of IP blocks used" (as opposed to the exponential growth in design-and-verification times that designers are experiencing with custom-designed hardware). Because of the increasing use of IP for SOC design, Compasano listed four critical aspects for commerical IP: functional correctness, inter-operability (to be achieved through standards), configurability, and ease of integration.
Professor Jari Nurmi’s keynote speech at SoC 2003 had a distinctly different, down-home flavor and covered the history of the event rather than focusing on design issues. One key piece of information was that the conference is held during Finland’s darkest and wettest time of the year because of the schedules of the three speakers at the first conference. This year, there were more than 40 presenters and panelists from both academia and industry and more than 180 attendees. One of the unique aspects of SoC 2003 was that it separated the industry and academic presentations, but did not run them concurrently. So the audience moved, en masse, between two presentation venues within Tampere Hall.
The academic presentations ran the gamut, from discussions of processors and processor architectures for SOC designs to algorithm development, software modeling, and IP-block interconnect. Among the processor papers were a 2-way VLIW adaptation of a SPARC core, presented by Dr Wonyong Sung of Seoul National University; an analysis and discussion of VLIW instruction scheduling from Dr. Kannappan Palaniappan of the University of Missouri-Columbia; a discussion of the COFFEE RISC core developed by TUT, which was presented by Professor Nurmi; and a presentation of a 2-processor chip design based on ARM processor cores and the AMBA bus, developed at ETRI in Korea. All of these papers demonstrated that substantial experimentation with processor cores for SOC design is ongoing. In his presentation, Dr. Palaniappan noted that the use of multiple processors in SOC design is bringing back mesh computing and other multiprocessor (MP) architectures first seen in the heyday of the supercomputer, however most of the processor presentations dealt with the use of non-homogeneous, multiple-processor SOC designs.
Besides efficient processing, one of the most difficult problems to solve is the interconnection of multiple processors and other large blocks on an SOC. Although several presentations dealt with modeling the complex protocols of intra-chip communications, one of the most interesting was "Managing On-Chip Communications" presented by Professor Timo Hamalainen of TUT, which included a case study of a communications protocol called HIBI (Heterogeneous IP Block Interconnection) developed at TUT. The HIBI interconnection scheme was developed 10 years ago as a board-level protocol to link FPGAs. HIBI has evolved over the ensuing decade and it moved on chip in 1997. The HIBI protocol is a good candidate for IP-block interconnect research because it has a flexible topology; it can be configured as a tree, ring, or bus.
Various projects using the HIBI protocol have produced some interesting conclusions. First, fixed interconnect topologies are well suited to fine-grained, algorithm-specific parallel processing applications but, in general, there is no optimal topology that can serve across a broad application range. Consequently, an SOC can either be designed using a fixed topology for a range of closely related applications or it needs a flexible interconnection scheme. Second, communications-centric experiments show that it’s important to exploit the application’s characteristics through the interconnection topology because that topology will have a large affect on performance. Finally, the HIBI team decided that although established parallel-processing doctrines can be applied to SOC design, the real challenge is effectively dealing with the need to perform heterogeneous computation.
Next year’s IP Based SOC Design Workshop in Grenoble will no doubt be held in late October or early November, as in past years. SoC 2004, held in Tampere once again, is already scheduled for November 15-18, 2004. For more information on the IP Based SOC Design Workshop and SoC 2004, go to www.design-reuse.com and www.cs.tut.fi/soc respectively.
