IP supports High-Speed USB host controllers
By Robert Cravotta -- EDN, December 11, 2003
ARC has announced two USB-host-controller IP (intellectual-property) offerings, the USB-HS SPH (single-port-host) and the USB-HS MPH (multiport-host) cores. The SPH core’s latency-based architecture sports the lowest gate count for a single-port, high-speed host controller and supports USB low-, full-, and high-speed (to-480-Mbps) data bandwidths. The core includes a functional subset of the HS-OTG (On the Go) IP core, is EHCI (Enhanced Host Controller Interface)-compatible, and supports UTMI (USB 2.0 Transceiver Macrocell Interface)+ and ULPI (Unit Level Prototype Implementation) PHYs (physical-layer interfaces). The USB host-specific controllers support programmable features, such as adaptive tuning, programmable fill level, and enhanced streaming, under software control.
The MPH IP core is a superset of the SPH product supporting two to eight controller ports. Each controller port is backward-compatible and can operate individually at high, full, or low speed. The integrated transaction translator enables a combined bandwidth of 480 Mbytes/sec for the high-speed ports to share and a combined bandwidth of 12 Mbytes/sec for the full-speed ports to share.
The SPH and MPH High-Speed USB cores are available as synthesizable, technology-independent VHDL or Verilog RTL source code, and they include simulation testbenches, synthesis scripts, USB software stacks, and class and device drivers. ARC offers PHYs and PHY macrocells that interoperate with the USB controllers through ARC’s CertiPHY program. The USB-HS SPH controller is available for licensing now. The USB-HS MPH controller will be available in fourth quarter of this year.
ARC, www.arc.com.
