Host-side controllers boost SATA speed, capabilities
By Brian Dipert -- EDN, December 25, 2003
Version 2 of the Serial ATA physical-layer specification, SATA II, is under development, and, just as recently occurred with the draft variant of 802.11g, silicon implementations are preceding its finalization (Picture). Marvell's four- and eight-port PCI-X (Peripheral Component Interconnect) host controllers, the 88SX6041 and 88SX6081, respectively, cost approximately $2.50 per port (100,000). The company's second-generation PHYs (physical layers) handle both 1.5-Gbps (SATA I) and 3-Gbps (SATA II) transfers, and spread-spectrum clocking minimizes EMI. Which stand-alone mass-storage device can deliver 3-Gbps speeds, aside from brief data bursts to and from on-drive RAM buffers, is not currently apparent. The controllers' support for multiple concatenated 1.5-Gbps streams (the so-called port-multiplier function, now finalized), however, clarifies the near-term applicability of the 3-Gbps mode.
The 88SX6041 and 88SX6081 also support other SATA II enhancements, such as native command queuing (also finalized). The chips are now in production and are software-compatible with Marvell's SATA I chips, and the company's API employs a SCSI-programming model that also supports future SAS (serial-attached-SCSI) development. The importance of SAS support depends on a belief that, between the ever-expanding SATA on the low end and FibreChannel for high-end applications, a need for SAS will still exist when it's finally unveiled. For more information, see my serial-storage-interface article in EDN's upcoming Jan 22, 2004, issue.
Marvell, 1-408-222-2500, www.marvell.com.
