FROM EDN EUROPE: A presence in the configurable DSP sector
By Graham Prophet -- EDN, June 10, 2004
ARM's OptimoDE is a configurable core based on technology acquired from Philips (out of the former Adelante, which had acquired the technology from Frontier Technology). Noting that standards are becoming "less standardised" (for example, witness the many varieties of video codecs). ARM describes the offering as a framework that produces a data engine, which you can program to run multiple variants of an application. The vendor also says you should view it as a configurable core plus tool set, rather than as a tool-based offering. The approach is algorithmcentric—you are configuring a signal-processing datapath using a VLIW-based approach with instruction lengths of 16 to 256 bits.
The tool set works from a base library of DSP functions and produces a C compiler for the resulting engine. You can trade silicon area, clock speed, and bit width for an optimum result in the design flow. You get a set of 14 typical starting configurations on which to build a design, which act as seeds for the optimisation process; size and arrangement of local storage and interconnect are also fully configurable. Profiling tools examine the operation of your code in a given configuration, identifying remaining areas for improvement and directing the optimisation. You can output to Verilog or to FPGA configuration code; a "shell" around the data engine handles interfacing to a system AMBA bus. An OptimoDE engine core can be as small as 9500 gates and can implement a 128-point FFT in 226 clock cycles.
In a separate announcement, ARM offered multiprocessing support with a synthesisable multiple core, the MPCore. The aim is to provide improved system-response time in complex multithreaded applications; with fewer processes running on any given core, you'll get quicker attention from the hardware. You can invoke four ARMv6 cores in an instance of MPCore, but the unit of IP remains the complete MPCore. It supports hybrid symmetry; that is, it can run symmetrical and asymmetrical multiprocessor code at the same time. You can therefore support existing asymmetric applications while writing newer code in a fully symmetric fashion. In the (up to) four-way cache structure, dedicated hardware maintains coherency. The MPCore looks to SOC design tools like a dual-AMBA-structured uniprocessor and is configurable with respect to the number of CPUs and interrupts and to whether floating-point support is included. The device has broadcast modes that software can use to address all CPUs within the processor, and it offers full software control of interrupts directed to the cores.
ARM, +44 1223 400400, www.arm.com.
