Interconnect takes center stage in pc-board design
By Gabe Moretti -- EDN, April 29, 2004
Many ASIC designers have had to cope with the fact that the physical characteristics of interconnect traces have become more important than gate characteristics. Now, pc-board designers are facing the same problem when designing high-speed systems. The Allegro platform from Cadence now supports designs operating at frequencies greater than 200 MHz by offering a co-design methodology that allows engineers to design, model, and analyze interconnect traces.
The new platform also supports team design. As one engineer changes a part of the circuit, all other members of the team can immediately observe the change. A designer can also protect his or her portion of the design by inhibiting the other members of the team from changing that design section. The platform provides these services for Package Designer and Package SI (signal integrity). These new products increase the number of functions of the Allegro platform to support design and analysis of system interconnect. Cadence states that he term "system interconnect" refers to the logical, physical, and electrical connection of a signal, its associated return path, and its power-delivery system.
A signal in a pc-board system travels between IC I/O buffers and traverses die-bump pads, package substrates, connectors, and pc boards. IC packages present a challenge for designers. At least in one case, an ASIC device that passed all tests in die form, failed when the designers tested it in its package because the impedance of the connection from the die to the pc board was greater than drive strength of the IC circuitry. Package Designer allows engineers to design the structures, like bump arrays and connectors, to provide connectivity between the die and the pc board. Designers can also evaluate various package types to choose the one with the appropriate electrical characteristics for the required operating conditions. Package SI provides the analysis tools to verify the signal integrity once you design the package and know the electrical characteristics of the I/O buffers on the die.
The platform runs on Windows, Linux, Solaris, HP-UX, and IBM AIX operating systems. The price for a one-year term license is $54,000 for Allegro Package Designer and $45,000 for Allegro Package SI.
Cadence, 1-408-943-1234, www.cadence.com.
