FPGAs pack a cost-conscious counterpunch
By Brian Dipert -- EDN, August 5, 2004
Xilinx's latest economy-minded FPGAs, the 90-nm-based Spartan-3 devices, are more than a year beyond their public unveiling and belatedly ramping into production, judging from the diminishing number of lack-of-availability complaints on Usenet newsgroup comp.arch.fpga and other industry forums (see “FPGA finesses a photolithography flip-flop,” EDN, April 17, 2003). Right on schedule, competitive responses from Altera and Lattice have hit the scene. Altera’s Cyclone II is the more evolutionary and, therefore, predictable of the two contenders. The company will begin by converting the lithography of its 0.13 micron-based Cyclone product line to a 90-nm process, akin to Xilinx’s shrinkage of Virtex-II to come up with Spartan-3 (see “FPGA takes a clean-slate approach to low prices,” EDN, Oct 17, 2002). It will then selectively add features, such as 250-MHz 18×18-bit multipliers, each also configurable as two 9×9-bit multipliers; dedicated DDR2 and QDRII memory-interface circuitry running at clock rates as fast as 167 MHz; and a slightly higher proportion of 4-kbit memory-to-logic blocks, balancing your desired features against each feature’s incremental die size, test time, and other cost increments.
As a result, Altera claims that its EP2C20 device, with 18,752 logic elements, will have a 24% smaller die than Xilinx’s 3S1000 with 15,360 logic elements. Die size is only one of several determinants of device price, but Altera’s silicon-slimming achievement is significant and brings up the question of how it will occur on a process that’s equivalent in lithography to Xilinx’s. Altera points to two primary factors: that the company made a conscious decision not to rush Cyclone II to market but instead to spend more time in chip design and layout and that Altera omitted some costly Xilinx-equivalent features, such as digitally controlled impedance and other exotic output-buffer circuits, from its chips.
Altera doesn’t expect engineering examples of the first member of the Cyclone II family, the EP2C35, to appear until next February, with the remaining family members rolling out in the subsequent six months (Table 1). The Cyclone II family is, again unfortunately, also not pinout-compatible with Cyclone, pushing your hardware prototyping feasibility into early 2005. Design-software support in the Quartus II tool set is now in place, however, including complete integration within the free Web Edition. The EP2C35 will cost $22 (250,000) at the end of 2005 in its smallest package and lowest speed grade.
Lattice, with its EC (Economy) and ECP (EconomyPlus) FPGAs, echoes Altera’s aggressive cost claims with the assertion that its 0.13-micron chips are comparable in die size to Xilinx’s 90-nm devices (Picture, Table 2). And you’ll be able to more readily test Lattice’s contentions, because it plans to ship the first devices, the $49 (1000) EC20 and $59 ECP-DSP20, in sample quantities beginning in July, along with companion design-tool suite support. The difference between EC and ECP variants of each product center on the ECP’s inclusion (at least in this initial implementation of the ECP concept) of 250-MHz sysDSP blocks, each of which contains a 36×36-bit multiplier that can alternatively operate as four 18×18-bit multipliers or eight 9×9-bit multipliers, along with addition, subtraction, and accumulate nodes. From an ispXPGA foundation, Lattice first shrunk the chips to the more advanced lithography and stripped out their embedded nonvolatile-configuration memory (see “RAM-transformed logic builds on a no-batteries foundation,” EDN, July 25, 2002). EC and ECP chips’ 275-MHz sysRAM blocks are also twice as large as in their ispXPGA counterparts, again to make more efficient use of silicon area, and, unlike with Xilinx’s Spartan-3, on which half of the LUTs (look-up tables) could find use as either logic or distributed RAM, only 25% of the LUTs on EC and ECP offer this flexibility. EC and ECP devices notably support industry-standard SPI-based configuration memories, along with traditional parallel and serial approaches.
Altera, 1-408-544-7000, www.altera.com.
Lattice Semiconductor, 1-503-268-8000, www.latticesemi.com.
