FROM EDN EUROPE: ARM, Synopsys bid to shape IP verification with "how-to" manual
By Graham Prophet -- EDN, March 4, 2004
If you work in purchased IP (intellectual property) for ASIC designs or in intracompany design-reuse programmes, your bookshelf may well include a copy of the Reuse Methodology Manual, co-authored by Synopsys' staff and other contributors from the IP and EDA communities and in its third edition since first publication several years ago. Now, Synopsys is attempting a similar exercise in the verification space, announcing that it will by midyear produce in collaboration with ARM a draft text of the Verification Methodology Manual.
Not surprisingly, given Synopsys' position on the system-level-languages debate, the company will structure the methodology around System Verilog. The intention, Synopsys says, is to produce a unified, fundamentally coverage-driven, verification scheme that will be defined in an open, standards-based way. It intends the scheme to be scalable and to allow verification at any hierarchical level of a design, starting at any level. Currently, industry offerings address the verification problem with myriad point tools, each of which comes with its own methodology and design flow; if you structure your efforts around a unified language, you can adopt a unified methodology, the company asserts. ARM's interest in the process is that, as an IP provider, it must deliver its products in a verifiable form, and it faces the problem of supplying to a market in which disparate verifications methods will be brought to bear. If there is no standard for writing verification files, providing verifiable IP will continue to be a problem, the company says.
The two companies hold out the promise of being able to carry out two to five times more verifications cycles for a given effort, minimising the amount of code you write, because much of what you might otherwise have written explicitly for elements such as testbenches is implicit in the SystemVerilog language. Nevertheless, the two companies say that the approach will allow for interoperation with IP defined in existing hardware-description languages and SystemC and will be adaptable to new techniques. Synopsys will implement the approach with Testbench and assertion building blocks in its Discovery Verification Platform, and its own DesignWare IP will become fully compliant with the methodology.
Synopsys, +1 650 584 5000, www.synopsys.com.
ARM; +44 223 400400, www.arm.com.
