EDN's 2003 Innovator/Innovation Program

EDN's editors have chosen this year's finalists from the scores of candidates in our annual Innovator and Innovation Program. Now we're calling on you to help select the winners.

By Staff -- EDN, February 5, 2004

EDN's editors have chosen this year's finalists from the scores of candidates in our annual Innovator and Innovation Program. See below to read detailed descriptions of the most innovative products and people of 2003.

In the spirit of innovation yet to come, we've also identified three companies that deserve special nomination as the Start-up of the Year.

EDN also prides itself on the depth and quality of its technical articles, whether staff-written or written by outside contributors. This year, we've added a new voting category: Best Contributed Article.

EDN is honoring the finalists and winners at a reception in San Francisco on March 29, where we will also announce the winner of our Open Circuit Contest. If you're already planning to attend the Embedded Systems Conference, we invite you join us in celebrating innovation. But you don't have to be at the show to attend our party. Click here for all the details.

INNOVATORS

AMD64 DESIGN TEAM LED BY FRED WEBER, AMD
It remains to be seen who will win the battle of 64-bit processors, but AMD clearly got a huge head start on Intel by staying with an architecture that’s compatible with Athlon and Pentium 32-bit processors. Chief technology officer Fred Weber challenged the four-part team to extend the x86 architecture for full application compatibility, increase the cache size and performance, integrate core-logic functions, widen the memory path, and integrate a high-speed chip-to-chip interconnect that came to be known as HyperTransport. The resulting Athlon 64 and Opteron processors can perform transparent and simultaneous 32- and 64-bit multitasking. The company has software-support commitments from Microsoft and from Linux providers. The design effort yielded compatible products for both the desktop and the server markets that could immediately run 32-bit operating systems and applications and that would minimize the effort of moving to 64 bits. And the HyperTransport technology has gained a life of its own, finding a home in products ranging from Microsoft’s Xbox to Cisco’s networking equipment. AMD, www.amd.com.

SHEN LIN, NORMAN CHANG, WEIZE XIE, AND YU LIU, APACHE DESIGN SOLUTIONS
This team set out to provide industry’s first full-chip dynamic physical power-integrity tool, critical for SOC (system-on-chip) design. Shen Lin and Norman Chang (both from HP Labs and both of whom hold doctorates from University of California—Berkeley) joined up with Weize Xie of HP Labs and Yu Liu, a Spice specialist from EDA vendor Anagram. Apache’s product, RedHawk-SDL, reflects two and a half years of effort and required a new physical database covering various methodologies; dynamic cell characterization; power-grid extraction; and reduction, including inductance, power analysis, and full-chip transient simulation. Overall, the complexity of the dynamic solution is 30 to 60 times that of static IR simulation.

To achieve these goals, the team developed a patent-pending "vectorless" dynamic solution. It based its design on statistical scenarios for propagation and switching, instead of using (unobtainable) worst-case power vectors, which would result in excessively long runtimes for full-chip level simulation. Its product has been proven with the successful design and implementation of TI’s first-ever 90-nm DSP. Apache Design Solutions, www.apache-da.com/.

NELLO SEVASTOPOULOS, LINEAR TECHNOLOGY CORP
Nello Sevastopoulos has spent more than two decades designing, refining, and evangelizing analog filters in IC form. He began his career at National Semiconductor, where he developed the industry-standard MF10 general-purpose switched-capacitor filter. Among his earlier accomplishments as a long-time LTC employee was his work in designing the industry’s first switched-capacitor lowpass filter to overcome the traditional dc-offset problem. (The device has received several patents.)

The LT1568 filter of 2003 is an ultra-low-noise, high-frequency filter building-block with predictable, repeatable performance that is well-suited for driving differential inputs of ADCs, among other applications. Sevastopoulos’s team also developed the first monolithic clock IC that users can program via an external resistor, which solved reliability and frequency-shift problems. He has also developed near-zero-drift, chopper-stabilized op amps with integrated sample/hold capacitors. Linear Technology Corp, www.linear.com.

ABHIJIT SHANBHAG AND ABHIJIT PHANSE, SCINTERA NETWORKS
Scintera Networks sought to find a way to get fiber or copper media to carry data at higher speeds than it was designed to handle. Essentially, the company needed a way to compensate for the signal distortions that the media introduced. And the company chose to work on the leading edge of technology at 10-Gbps speeds. DSPs have often found use in compensation roles, but Scintera engineers Abhijit Shanbhag and Abhijit Phanse found that no DSP that could handle the task at 10 Gbps—especially when the compensation engine had to be blindly adaptive to the distortion in the media, factors such as temperature, and a variety of time-varying channels. So the duo set out to design a custom signal-processing platform for the task at hand. The result is the ASSP (Advanced Signal Processing Platform). It is the core of the company’s electronic-dispersion-compensation engine, which allows 10-Gbps rates over fiber designed for 1-Mbps rates. The ASSP architecture features a closed-loop design that compares the actual characteristics of a signal with the desired characteristics and then makes compensations in the signal-processing front end. The initial dispersion-compensation engine the company has announced will allow scores of enterprises to move to 10-Gbps rates without going to the expense of installing new fiber. Scintera Networks, www.scinteranetworks.com.

ANALOG FUNCTIONS

AD8099 OP AMP

Decades of op-amp design used fundamentally the same input structures. Input-architecture variations lead to compromises among distortion, noise, dc precision, power, and speed. But significant performance improvements derived more from fabrication-process innovations than from the rare topological advance.

For example, op-amp designers linearize the input transconductance to minimize distortion. But the traditional linearization methods increase noise. The AD8099’s novel input structure improves on this longstanding trade-off with a common-mode linearizing circuit without sacrificing differential-mode performance. Similarly, the 8099 minimizes noise and dc errors without sacrificing speed and linearity, or increasing power dissipation. The amplifier offers a tenfold reduction in wideband distortion and a three-times improvement in slew rate over competing 1-nV/ amplifiers.

The 8099’s novel pinout lowers mutual inductances, reducing distortion products caused by coupling between input and supply pins. A second output pin cuts down on feedback parasitics, eases board layout, and increases the stability of the AD8099. Analog Devices, www.analog.com.

LT1568 MATCHED FILTER

Linear Technology’s LT1568, an ultra-low-noise, high-frequency filter building block, targets antialiasing or reconstruction applications operating at 200 kHz to 10 MHz. You can use the LT1568 and low-cost external resistors to implement accurate lowpass, bandpass, highpass, roofing, or notch filters with Bessel, Butterworth, Chebyshev, Bessel, or elliptic responses. Most important, you can construct matching multichannel filters, such as those required for I/Q channel pairs, without production trimming.

The 1568 uses on-chip trimmed capacitors, thin-film resistors, and 1.5-nV/ op amps in a novel filter topology to realize matched two-pole filter pairs with 92-dB SNR, –84-dB THD, and 0.25-dB channel-to-channel matching. The filter maintains its performance over temperature, with the cutoff frequency varying by only 1 ppm/°C.

The LT1568 temperature compensates its internal amplifiers’ gain bandwidth, so errors caused by their finite speed are repeatable and correctable. The filter’s performance is repeatable from channel-to-channel and part-to-part allowing cascades the two-pole sections. Linear Technology, www.linear.com.

LMV1012 MICROPHONE AMPLIFIER

Circuit-board space has always been scarce. But portable products put such premiums on physical dimensions that designers sweat every cubic millimeter. Portable products incorporating small ECMs (electret condenser microphones) save space with National Semiconductor’s LMV1012 amplifier. The LMV1012 replaces the JFET buffer, offering greater battery life, noise immunity, and microphone performance.

The LMV1012 fits into the ultraminiature ECMs that mobile handsets, headset accessories, PDAs, and other portable devices use, resulting in increased sensitivity and lower supply current. The amplifier connects directly to two-wire ECMs to provide 17-dB gain and improve RF immunity and distortion. LMV1012-equipped ECMs offer THD of 0.1%, SNR greater than 55 dB, and supply current less than 240 µA.

The LMV1014 mates with three-wire ECMs. This gain stage draws less than 40 mA and provides a 200O output impedance, power-supply rejection ratio greater than 60 dB, and SNR that bests 55 dB. Both amplifiers meet existing ECM standards. National Semiconductor, www.national.com.

SIL9190 AND SIL9993 CHIP SET

Silicon Image’s SIL9190 transmitter and SIL9993 receiver form a high-bandwidth HDMI (High-Definition Multimedia Interface) to simultaneously carry uncompressed high-definition video and compressed multichannel audio. The chips support graphics modes specified in the DVI standard and PC graphics modes up to XGA (1024×768 pixels). The chips convert between RGB and YCbCr, so end users can connect PCs and monitors interchangeably with DVD players and televisions.

To carry synchronized audio and video over a single link, the SIL9993 extracts audio using a new audio PLL to ensure no audible discontinuities in the audio stream, and transfers audio data during the video blanking interval to prevent interference between the two signals. The device carries audio as either stereo PCM or compressed format over an SPDIF.

Both parts implement HDCP (high-bandwidth digital copy protection). On-chip HDCP keys eliminate the OEM’s burden of providing a secure key-data link. Silicon Image, www.siliconimage.com.

 

APPLICATION-SPECIFIC STANDARD PRODUCTS/SOCs

AT43USB370 USB HOST PROCESSOR

USB has been successful in the PC world, but it is difficult to implement when a non-PC device must operate as a host. Microsoft and peripheral makers have spent years perfecting the drivers for popular PC peripherals. Devices such as digital cameras, however, typically lack the drivers needed to connect directly to a printer or other peripherals and must instead connect via a PC. Atmel attacked the USB-host problem with the AT43USB370 processor by developing a set of APIs that support most popular classes of USB peripherals. Because the APIs come in binary form and run on the Atmel chip, the development team can choose any processor or operating system to handle the primary application in a product design. Moreover, the chip is based on dual-RISC cores that completely offload the need for the application processor in a product to handle USB chores. And at less than $5 (high volumes), the processor yields savings in development time that make the dedicated USB processor affordable in any application in which you need host functions. Atmel, www.atmel.com.

BLUECORE3-MULTIMEDIA

Although proponents overhyped it early on, Bluetooth wireless technology has become pervasive in target applications, such as cell phones. The wireless personal network can connect a cell phone to a PC for contact synchronization or connect wirelessly to a headset. But developers of most Bluetooth chips designed them for a narrow range of applications. CSR (Cambridge Silicon Radio) took the opposite approach with the BlueCore3-Multimedia IC by adding a programmable DSP that design teams could harness to develop compelling new products. The company is offering DSP-software support for a number of audio applications, such as echo cancellation and noise-reduction algorithms. The chip also includes a 16-bit stereo codec. Wireless headphones for music are one potential application, and those of you who have tried the wireless headphones on the market know that an upgrade is in order. CSR claims that its chip will wirelessly support 128-kbps MP3 sounds—sometimes referred to as "CD quality." The Bluetooth implementation meets the Version 1.2 spec and the adaptive frequency-hopping technique that allows Bluetooth and 802.11 radios to operate in the same area. Cambridge Silicon Radio, www.csr.com.

DIMENSION 8650 (DMN-8650) SINGLE-CHIP HDD/DVD-RECORDER-SYSTEM PROCESSOR

Fans of personal video recorders, such as TiVO, are devout, and doubters lament only the lack of removable media upon which they can store programs. This past holiday season witnessed an answer for the masses: a digital video recorder with both a hard disk and a DVD burner. And that’s precisely the product that the DiMeNsion 8650 from LSI Logic makes possible. The chip integrates dual MIPS cores; MPEG and DV video codecs; and a spate of popular audio codecs, including MP3 and Windows Media Audio. Other features include an audio DSP, an IEEE-1394 FireWire interface, an ATAPI interface for hard disks and DVD drives, and a 2-D graphics engine. A preprocess motion-compensated temporal filter combines with a postprocess motion-control deinterlacing routine to optimize video. Among other modes, the design allows an end user to watch a DVD while recording a show to the hard disk, copy a program from the hard disk to a DVD, and time-shift programs. The chip sells for less than $30 (high volumes). LSI Logic, www.lsilogic.com.

AR7 ADSL ROUTER ON CHIP

Broadband connectivity may not have taken off fast enough for some pundits, but the consumers that bought broadband didn’t take long to figure out what was possible with a router. Indeed, a shared broadband connection has been a key driver of home networking. But home networks come with too many boxes. Texas Instruments, however, has enabled manufactures to integrate the router and DSL modem—ultimately reducing the price that consumers pay for gear. The AR7 is a single chip, not a multichip module. The device even integrates a 12V line driver yet is made in pure CMOS. The integrated line drive pays off in a much simpler analog front end and yet another reduction in the bill of materials. Other features include programmable digital transmitting and receiving filters, dynamic adaptive equalization, integrated power regulators, and a 10/100 Ethernet PHY. The company also offers a four-port Ethernet switch chip and an 802.11 wireless chip that you can mate with the modem/router. Texas Instruments, www.ti.com.

GENERATION9 INTEGRATED DIGITAL-TV SYSTEM

HDTV technologies have finally begun to sell, as broadcasters offer more and more content in the compelling 1080i format. Now, TV and set-top-box vendors need highly integrated digital-TV chips to affordably manufacture new products. The Generation9 digital-TV chip sells for less than $50 (high volumes) and needs only memory and a network interface to comprise a complete system. Moreover, the Generation9 chip offers features that designers can tap to deliver truly differentiated products. For instance, the chip can simultaneously drive two displays or TVs. The on-chip Texture Processor and Warp Engine support realistic graphics and compelling user interfaces. A 64-bit MIPS CPU combined with a programmable-DSP core allows design teams to add features via software, yet Zoran offers software reference platforms that jump-start development. The chip includes encryption and content-protection mechanisms, and you can use them in regions around the world. The design can also support personal-video-recorder applications for both standard-definition and high-definition content. Zoran, www.zoran.com.

COMPONENTS

D6F GAS-FLOW SENSOR

The D6F gas-flow sensor from Omron is not just an embodiment of a conventional sensor in micromachined form. Instead, it takes advantage of MEMS (microelectrical-mechanical systems) to incorporate an active temperature sensor for faster sensing, rather than a passive, usually resistive, bridge sensor. It can measure flows as low as 1 cm/sec and is suitable for natural-gas, HVAC, fuel-cell, and medical applications. The sensor uses a heater and pair of opposing temperature sensors as a thermopile to generate a voltage based on the differential temperature between the sensors; this difference is due to the mass flowing between them. Only the silicon base, silicon-oxide isolation layer, and electrode pad are exposed to the surface and gas under measurement. Further, as a MEMS device, the die measures just 1.5 mm sq, and the final packaged device measures 10×7 mm, far smaller than discrete versions, and includes on-chip temperature compensation. Omron, www.omron.com.

GEOHELIX-S ACTIVE GPS ANTENNA

Using a quadrifilar helix—the optimum structure for GPS reception—Sarantel’s Geohelix-S active antenna achieves miniaturization by loading the antenna with a high-dielectric ceramic. It also integrates a 40-dB isolation balun, converting single-ended feed to balanced, so it needs no ground plane on the pc board. The antenna creates a small near field, which resonates to create the far-field radiation pattern by using the twists in the loops of the structure and using high-dielectric material. As a result, it yields no energy to a user’s hand or head, and the reception pattern is nearly the same as it would be in free space. Sarantel, www.sarantel.com.

LIS3L02 THREE-AXIS LOW-g ACCELEROMETER

STMicroelectronics’ LIS3L02 micromachined accelerometer is a three-axis device that can measure down to 30 µg of acceleration and provides analog and digital output. To achieve this performance, the company developed in-plane and out-of-plane micromechanical structures with epitaxial-growth and grinding processing steps to provide 20-µm-thick structures with low mechanical stress. A high-yield-strength epitaxial polysilicon layer, which the company also developed for this device, provides further robustness. Other process enhancements include two-level polysilicon layers and high-aspect-ratio etching. These features provide low cross-axis sensitivity, thinning of the silicon die, and stacking of the sensing element. These developments yield a two-chip device in a 1.8-mm-high, 7×7-mm-footprint package; it operates from 2.7V at 2 mW and withstands as much as 20,000g of shock. STMicroelectronics, www.st.com.

DIGITAL ICs

HARDCOPY STRATIX

The silicon concept behind Altera's HardCopy Stratix isn't new; prior-generation Apex 20K-based parts were unveiled in late 2001. What is new is your ability to directly compile your design to HardCopy devices. In the past, you would first create an FPGA-housed prototype, then ship the configuration bit stream to Altera for conversion. In effect, this bypass-the-FPGA capability, enabled by latest versions of Altera's Quartus II design software with its HardCopy Stratix-tuned floorplanner and timing models, expands the company beyond its programmable-logic roots and into the structured-ASIC arena.

Mask-programmable HardCopy die can be as much as 70% smaller than FPGA counterparts. HardCopy chips deliver higher performance and lower current draw than their FPGA complements in most real-life designs; power- and performance-estimator utilities enable you to predict the improvements. After you meet the design requirements and Altera accepts the design, the company's HardCopy conversion process takes less than three weeks. After you approve the timing results, HardCopy prototypes will be available within five weeks, and production units will appear within eight weeks of prototype approval. Until then, you can, if necessary, ship system designs with FPGAs inside. Altera, www.altera.com.

ACCELARRAY

Structured ASICs represent manufacturers' responses to customers' requests for parts with traditional ASIC-like high speed, high density, low per-gate cost, and low power consumption but without ASICs' increasingly high NRE (nonrecurring-engineering) costs and lengthy delays from design completion to first chips in hand. Whereas most vendors are manufacturing their structured ASICs on trailing-edge process technologies, Fujitsu's AccelArray devices push the lithography envelope by virtue of their fabrication on leading-edge 0.11-micron and, later this year, 90-nm manufacturing lines.

The AccelArray architecture offers three (of six total) design-customizable metal layers and predesigned global clock trees, both factors greatly simplifying the manufacturing process. Back-end physical design can wrap up in two to four weeks, and you can receive prototype chips in as few as eight weeks. Fujitsu targets designs with yearly volumes of 5000 to 100,000 units. AccelArray designs deliver 333-MHz core system frequencies, with 800-MHz analog PLL capability and as many as eight clock domains available, and they support gate counts of 512,000 to 3.8 million. The company offers a broad family of embedded SRAM cores in both single- and dual-port variants, and the metal-programmable I/O buffers handle a range of industry standards, including support for source-synchronous memory buses. Fujitsu, www.fma.fujitsu.com.

MOBILE DISKONCHIP G3

As its name implies, G3 isn't M-Systems' first DiskOnChip generation, but the latest product family's low power consumption and diminutive packaging are notable, and its embrace of low-cost MLC (multilevel-cell) NAND flash technology is a first-time achievement. And a significant achievement it is—operating stand-alone, MLC NAND flash memory's low reliability would make it unacceptable for most code- and data-storage applications. Software-based EDAC (error detection and correction) running on the system CPU, however, would be too performance- and power-sapping. Instead, M-Systems embeds EDAC within the memory controller that shares space with the NAND array on the chips' die.

The result, M-Systems claims, is devices that deliver only one fault per 10¹³ Mbytes' worth of written information, a bit-error figure many orders of magnitude better than even SLC (single-level-cell) NAND flash memory. Mobile DiskOnChip G3 parts, in 512-Mbit and (soon) 1-Gbit densities, come in 7×10×1.2-mm FBGA packages. Dual 16-bit internal data buses and a corresponding dual-plane NAND array boost sustained read and write speeds, and a 2-kbyte boot block enables system initialization and DMA-accelerated transfer of additional portions of the Mobile DiskOnChip's code contents to system RAM for subsequent execution (a system-memory architecture reminiscent of a PC's BIOS-plus-HDD-plus-DRAM multitiered approach). Elaborate write-protection features safeguard against inadvertent alteration of stored information. M-Systems, www.m-sys.com.

 

EDA: DESIGN EXPLORATION

SPYGLASS CONSTRAINTS VALIDATION TOOL

In addition to a netlist, the constraints file is an essential input to any synthesis tool. The constraints set has increased in complexity and importance with processes smaller than 250 nm. Yet designers have lacked the tools to verify and manage the constraints. Atrenta’s Spyglass Constraints tool checks and validates design constraints along with the design. It reads either the RTL (register-transfer-level) or gate-level netlist and one or more SDC (Synopsys Design Constraints) files and verifies the constraints information for correctness and completeness against the design at the block level, at the chip level, and between the blocks and the chip. The tool employs predictive-analysis techniques to perform fast synthesis, which allows it to foresee downstream engineering and manufacturing issues, so it can advise designers of problems even before they synthesize the design. Atrenta, www.atrenta.com.

TIME DIRECTOR RTL-TIMING-ANALYSIS SOFTWARE

The electronics industry has been trying to achieve RTL (register-transfer-level) sign-off for a few years. One of the obstacles to achieving the goal was the absence of timing closure. Time Director, from InTime Software allows designers to perform static-timing analysis at RTL, instead of having to use gate-level models. The tool also offers a debugging environment that supports hierarchical analysis and cross-probing, allowing designers to quickly modify the circuit description to fix any timing problems. The product works by reading the RTL code, timing constraints, and a design kit that it generates from the target library. Time Director also provides block-level area estimates to help the design team plan for downstream packaging, data-flow, and floorplanning issues. InTime Software, www.intime-online.com.

LINK FOR MODELSIM COSIMULATION ENVIRONMENT

Language-based attempts to close the gap between algorithmic exploration and hardware-implementation simulation have either fallen short or are in the early development stage. The Mathworks, in collaboration with Mentor Graphics, has developed a solution that allows designers to concurrently simulate both algorithms and hardware implementations. The integrated cosimulation environment provided by Link for ModelSim significantly narrows the gap between algorithm and hardware implementation by adding either Verilog or VHDL to the simultaneous direct mixed-language-simulation capabilities of Matlab and Simulink. Designers can eliminate the costly errors and development time that are associated with the manual translation and verification required to synthesize from the architectural level to the register-transfer level. The Mathworks, www.mathworks.com; Mentor Graphics, www.mentor.com.

SYSTEM ARCHITECT DESIGN-VERIFICATION SOFTWARE

System architects are challenged in making design trade-offs by having to evaluate an implementation at different levels of abstraction using different and often-incompatible design representations. System Architect allows engineers to profile and analyze architecture metrics from the specification phase down to the RTL (register-transfer-level) phase. It provides a set of SAIFs (System Architect Instrumented Functions), which engineers use to instrument functional code or develop token-based models that describe high-level system transactions. After simulation of a design, designers can run a statistical analysis of the results and visualize, both in graphical and report form, the functional and hardware resource trade-offs they use to accept or modify the design architecture. During functional simulation, engineers can use the SAIFs to profile transactions, bus usage, throughput and latencies, interrupt-response times, and cache hits and misses. Summit Design, www.summit-design.com.

 

EDA: PHYSICAL ANALYSIS

REDHAWK-SDL FULL-CHIP SOC DYNAMIC POWER INTEGRITY SOLUTION

Dynamic integrity of power-supply networks has become one of the most critical issues facing IC designers. Increasing complexity and leakage, faster edge rates, decreasing supply voltages, and low-power design techniques have contributed to the rise of design failures. You must verify the full-chip dynamic effects from simultaneously switching outputs in the core and I/O regions and their impact on timing before tape-out. RedHawk-SDL provides a vectorless dynamic solution for full-chip verification of transient voltage drop. Driven by static-timing-analysis windows, it uses propagation and switching statistics instead of vectors, improving coverage and decreasing analysis time. The tool provides transistor-level accuracy by Spice precharacterization of switching-current profiles, transistor-intrinsic parasitics, and cell-delay impacts from dynamic voltage drops. Combining the models with a full-chip power/ground RLC network extraction based on a patent-pending effective-loop inductance method, RedHawk-SDL provides an accurate analysis of inductive noise. Apache Design Solutions, www.apachedesignsolutions.com.

BLAST RAIL POWER-INTEGRITY TOOL

Whenever the industry moves from one process technology node to another, power constraints tighten to maximize device performance and reliability. Blast Rail performs concurrent analysis and optimization of power, voltage drop, and timing, enabling efficient power management. The tool also offers other capabilities, such as visibility into power and voltage distribution early in the design flow to enable better floorplanning decisions. Blast Rail uses the same engines (power, rail, and timing analysis) throughout the design flow. Its power-grid synthesis provides guidance in determining optimal power grids, saving routing resources and reducing chip area. The tool performs transient simulations, identifies instantaneous voltage drops due to power surges and simultaneous switching, and provides a mechanism to more efficiently add decoupling capacitances. Magma Design Automation, www.magma-da.com.

COOLTIME ELECTRICAL-INTEGRITY SUITE

Power-distribution modeling is a major challenge in IC design, particularly when you’re dealing with the impact of voltage drops on timing, power, and noise throughout the chip. Cooltime concurrently analyzes all electrical aspects of a design, taking into account their interdependence. The product includes analysis of power, dynamic voltage drop, electromigration, timing, and signal integrity. Also embedded in the tool is a complete power grid and signal net extractor. User input on decoupling capacitors and package parasitics allows the tool to take into account their impact on the total voltage drop. You can then use the derated voltages at each instance to recompute the delay and noise margins. Sequence Design, www.sequencedesign.com.

MEASUREXTRACTOR MODELING TOOL

The behavior of interconnect wires has greater impact on the functions of most designs than the logic modules they connect. Engineers spend a lot of time simulating, verifying, and correcting this behavior. In addition, it is often difficult to input data obtained from test instruments into EDA tools. The MeasureXtractor modeling tool accepts measurement data from either time- or frequency-domain instrumentation and converts it into a model compatible with Spice or IBIS simulation tools. The tool uses algorithmic passivity constraints to enable designers to include interconnect data in the system simulation. Engineers can then predict losses, dispersion, jitter, crosstalk, and reflections due to interconnect geometry and evaluate the impact of frequency-dependent effects on the design implementation. TDA Systems, www.tdasystems.com.

 

EMBEDDED PRODUCTS

CORNICE SE EMBEDDED SUBSYSTEM

A new 0.5-in.³ embedded storage subsystem from Cornice offers bulk storage at a price lower than that for flash-memory and miniature drives. The first-generation Cornice SE features 1.5 Gbytes of storage, which is roughly equivalent to 30 compact discs of music or two hours of VHS-quality MPEG digital video. The new rotating magnetic storage design provides battery usage similar to solid-state storage media and is rugged enough to withstand a 1m drop onto solid concrete. Samsung, RCA, Rio, iRiver, Creative, and others have introduced portable consumer products based on Cornice’s technology. By eliminating elaborate caching, buffering mechanisms, and redundant components, Cornice has reduced the SE to 31 electrical components and three ICs, compared with the 110 components and six ICs in competitive storage products. It has also reduced assembly time to less than 2 minutes. The 1.5-Gbyte Cornice SE sells for $65 (100,000). Cornice, 1-303-651-7291, www.corniceco.com.

TETRA CPU BOARD

Equator Technologies introduced the Tetra CPU Board, a low-cost, small-form-factor platform for running C-based, real-time video/audio applications. With its VLIW (very-long-instruction-word)-processing technology, the Tetra CPU Board achieves 40 billion operations per second—enough to run complex video and audio algorithms along with real-time operating systems, such as Linux, VxWorks, and eCos. With a system cost of just $89 and a size no bigger than a deck of cards, the Tetra still runs a wide array of video-centric software. For example, the Tetra CPU board’s available codecs include H.264 and the WM9 (Windows Media 9) Series player (SD and HD) and WM9 Series A/V encoder. The Tetra CPU Board has been applied to video thin clients, such as airplane and automobile in-seat-entertainment displays, Ethernet-based televisions, video-conferencing systems, video-surveillance equipment, and other wired and wireless products. Equator Technologies Inc, 1-408-369-5200, www.equator.com.

I-BEANS TINY MODULES

Millennial Net’s self-contained, miniature i-Beans computer comes with a built-in power source, flash memory, a digital-I/O interface, A/D and D/A converters, and an RF transceiver for bidirectional communication. By adding the appropriate sensors, you can use i-Bean hardware and software to create self-organizing, wireless-sensor networks for building automation, security, remote-health-monitoring, and other applications.

With a form factor about the size of a dime, an i-Bean device runs for as long as 10 years on a 3V-dc coin battery. Self-organizing, self-healing, multipoint-to-multipoint communications protocols eliminate the need for network administration and configuration. Simply turn on the device, and data automatically routes through the best possible path through i-Bean Routers back to the i-Bean Gateway.

Millennial Net offers a $4500 evaluation kit that includes five i-Bean transmitter/receivers, three i-Bean Routers, and one i-Bean serial Gateway along with accompanying software and documentation. Millennial Net Inc, 1-617-225-0100, www.millennial.net.

SMT319 GRAPHICS MODULE

Sundance’s SMT319 imaging module provides a flexible architecture for video capture, processing, and display. The module conforms to the TIM-40 form factor and offers two channels of video input, two channels of video output, and enough processing power to perform many imaging operations in real time. The design uses proprietary high-bandwidth point-to-point data-transfer links to avoid the traditional bottlenecks that shared bus structures or shared memory cause. The module can also gain additional processing power or specialized functions by combining with other modules to create multiprocessor networks. The SMT319 uses the TMS320C6414 DSP with a maximum clock speed of 600 MHz and a 64-bit external data bus. The module also includes a Xilinx Virtex-II FPGA. This combination delivers the FPGA’s parallel-processing features for power-hungry algorithms, and the DSP supports the more complicated sequential algorithms and control structures. The SMT319 is priced at $2995. Sundance, 1-775-827-3103, www.sundance.com.

EBC-C3 FANLESS SINGLE-BOARD COMPUTER

WinSystems’ EBC-C3 integrates desktop-PC technology into the harsh environments of industrial applications. This 733-MHz Pentium-compatible single-board computer with a –40 to +85°C operating temperature allows industrial designers to take full advantage of x86-compatible operating systems, application programs, or networking technology. The company bases the EBC-C3 on the 733-MHz VIA fanless Eden ESP7000 processor and supports as much as 512 Mbytes of PC133 SDRAM. It also supports type I or II Compact Flash cards with as much as 1 Gbyte of solid-state storage. A separate 32-pin socket accepts an M-Systems DiskOnChip flash device, SRAM, or EPROM. Dual Ultra DMA 33/66/100 hard-disk interfaces and a 3.5/5.25-in. floppy-disk controller support rotational media. The EBC-C3 is a small, EBX-compatible board that provides a range of I/O options, including Ethernet, USB, and differential serial expansion. WinSystems verifies compatibility with Windows XP embedded, Windows CE.NET, Linux, and other PC-compatible software. The EBC-C3 sells for $695 (moderate volumes). WinSystems, 1-817-274-7553, www.winsystems.com.

 

NETWORK AND COMMUNICATION CHIPS

HARRIER 10/100/1000 MULTIPORT ETHERNET MAC

Gigabit Ethernet has come to the desktop with most business-class PCs that vendors are now shipping with the faster network interface. But the switches that connect Gigabit clients don’t handle full-line rate traffic other than in bursts. So, network-gear designers will rely on so-called oversubscription techniques in routers and switches, where the aggregate potential bandwidth is less than the sum of the connected ports. Oversubscription saves dollars yet provides the data rates that clients need. Ample Communication pioneered oversubscription techniques and its Harrier 10/100/1000 Ethernet MAC (media-access-controller) aggregation device supports 24 Ethernet ports. Design teams can use the chip in full-line-rate applications or with aggregate speed oversubscribed from 2-to-1 to 4.8-to-1. Gear designs can combine a 24-port Harrier chip with a single 10-Gbps network processor or switch fabric, providing a 40% reduction in cost relative to full-rate designs. Meanwhile, the Harrier chip integrates a QOS (quality-of-service) scheme to ensure that priority traffic always gets full-rate service. Ample Communications, www.amplecomm.com.

BCM4317 AIRFORCE ONE CHIP

It’s no rarity these days to see a notebook computer with an 802.11 wireless LAN, but the technology thus far has been too expensive, power-hungry, and big for smaller hosts, such as cell phones. But 802.11 will unquestionably come to such devices. Broadcom is now delivering the first single-chip 802.11b implementation for small portable devices. The AirForce One chip integrates the 2.4-GHz radio, baseband processor, MAC (media-access controller), power amplifier, and other radio components using a mainstream CMOS process. The company claims that a module with the IC and a handful of discrete components is 87% smaller than competing designs and uses 97% less power than other 802.11b modules. Target products include cell phones, PDAs, digital cameras, and MP3 players. Broadcom also offers a single-chip Bluetooth implementation you can combine on a module with the AirForce One chip. Broadcom, www.broadcom.com.

MB87Q3050 10-GBPS ETHERNET-SWITCH-CHIP IC

The continued explosion of multimedia data on the Web has led to the deployment of 1-Gbps Ethernet on the desktop—especially in data-center clusters—and therefore will require the uplink for these clusters to move to 10-Gbps technology. Fujitsu is leading the push to 10-Gbps Ethernet with the MB87Q30050, which integrates a 12-port switch. Looking back, 10-Gbps Ethernet switches have been board-level modules that cost $20,000 or so and resided in a $250,000 system. The Fujitsu chip costs around $200 and will bring system cost down to less than $5000. The switch core features a credit-based flow-control scheme and packet-by-packet operation with lengths variable from 64 bytes to 9 kbytes. Cut-through forwarding and buffer management for the variable-length frames reduce latency and minimize store-and-forward operations. The chip offers nonblocking aggregate performance of 240 Gbps with wire-speed operation at each port. It also includes a SERDES for each port and an on-chip memory buffer, and it implements QOS (quality-of-service) and packet-classification features. Fujitsu, www.fma.fujitsu.com.

SCN3142 ELECTRONIC-DISPERSION-COMPENSATION ENGINE

With desktops moving to 1-Gbps Ethernet and the explosion of data volume continuing, enterprises must explore using 10-Gbps Ethernet in LAN backbones and in storage-area networks. But many installations that are otherwise ripe for 10-Gbps speeds lack the cable plant to support the faster data rates. So Scintera Networks set out to find a way to run 10-Gbps Ethernet over multimode fiber designed for 1- or 2-Gbps rates. At the higher rates, dispersion on the fiber raises the bit-error rate to unacceptable levels. Scintera’s answer is the SCN3142 electronic-dispersion-compensation engine. The company built the device in a mainstream CMOS process and bases on its Advanced Signal Processing Platform. When you place it at the end of a 300m cable, the IC reverses the dispersion distortion on a 10-Gbps signal. And the company claims that the chip’s 300m range covers 80% of the multimode-cable plant, meaning that most companies need not invest in expensive new cabling. Moreover, the technology is fully transparent to protocol, transmission techniques, and the people that work on such optical networks. Scintera Networks, www.scinteranetworks.com.

POWER ICs

XPHASE SCALABLE POWER-MANAGEMENT CHIP SET

International Rectifier’s xPhase chip set forms a scalable architecture that allows you to add or remove phases of a dc/dc buck converter. The IR3081 control IC contains all of the one-per-converter circuitry, including VID (voltage identification), PWM ramp oscillator, error amplifier, bias source, and fault detection. The control-and-phase ICs connect through a five-wire bus that communicates the bias, timing, average current, error-amplifier output, and VID voltage. Eliminating point-to-point wiring shortens the control-to-phase IC interconnections, reduces parasitics, and simplifies layouts.

The IR3086 phase IC contains all the one-per-phase circuitry, including the gate drivers, PWM comparator and latch, overvoltage and overtemperature protection, and current sensing and sharing. The phase IC provides body braking, a synch-FET timing feature that improves transient response and efficiency when load current significantly decreases. You can use a larger inductor, which improves the overall efficiency, and a smaller output capacitor, which saves cost and space. International Rectifier, www.irf.com.

X3015P POINT-OF-LOAD POWER CONVERTER

The X3015P integrates 22 power-semiconductor and layout-critical passive components into a 10×12-mm LGA package, reducing the size and increasing the reliability of a nonisolated dc/dc converter. Programmable fixed-frequency operation allows you to optimize your selection of output-filter L and C components.

The X3015P provides 15A at 0.7 to 4V dc. The programmable output voltage allows you to use one part for a range of applications. The 1.5-mm height permits bottom-side mounting, freeing valuable topside board area.

A current density over 80A/sq in. allows you to use the X3015P in IBA (Intermediate Bus Architecture) as well as point-of-load applications. The converter carries a UL approval. PowerOne, www.power-one.com.

RHFL4913 RAD-HARD LOW-DROPOUT REGULATOR

STMicroelectronics collaborated with CERN (Conseil European pour la Recherché Nucleaire) to develop the 3A, rad-hard RHFL4913 positive-low-dropout voltage regulator with output inhibit. This device comes in a hermetic package and targets space applications that need radiation-tolerant ICs.

The RHFL4913 is fabricated in a radiation-tolerant BiCMOS process. Circuit methods compensate for the decrease of device beta measurable on postrad samples. The IC blocks postrad leakages without sacrificing IC performance.

The RHFL4913 exhibits a high tolerance to radiation, including 300 krad at 0.01 rad/sec, SEL (single-event-latch-up) testing, and SEU (single-event upset) to 68-MeV (mega electron volts) LET (linear-energy transfer). The regulator provides low dropout voltage and power dissipation, essential for satellite power management and system efficiency. The chip allows monitoring and remotely controlling static- and dynamic-overload conditions, including latch-up caused by single-event effects. It provides optional overtemperature, overvoltage, and overcurrent protection; short-circuit control; and remote sensing. STMicroelectronics,www.st.com.

POWER SUPPLIES

TYPHOON BRICKS DC/DC CONVERTERS

Artesyn's Typhoon series of dc/dc converters provides high-density isolated dc-dc power conversion for point-of-load-communication applications. Based on a new topology, the converters use primary- and secondary-side microcontrollers that provide an intelligent way of handling input overvoltage conditions. The Typhoon series provides high levels of transient current performance by measuring and controlling the output voltage on the secondary side and eliminating traditional hindrances to high-speed performance, such as optocouplers. Artesyn Technologies, www.artesyn.com.

B048K120T20 V*I CHIP BCM

The V*I Chip BCM (bus-converter module) from Vicor provides an isolated intermediate bus voltage from a narrow-input-range dc source to power nonisolated point-of-load converters. The BCM uses the new SAC (sine-amplitude-converter) topology, which operates at a switching frequency of 3.5 MHz, an order of magnitude higher than the operating frequency of typical pulse-width-modulated converters as deployed in isolated dc/dc-converter bricks. The high switching frequency enables a BCM to use only 0.85×1.26 in. of board space and attain a high power density of 800W/in.³Vicor Corp, www.vicorpower.com.

 

PROCESSORS

ATHLON 64 MICROPROCESSOR

The AMD Athlon 64 processor architecture natively supports both 32- and 64-bit x86-compatible processing. In 64-bit mode, the Athlon 64 processor can support full, transparent, and simultaneous 32- and 64-bit-platform application multitasking. It extends the physical-address space to 1 Tbyte of installed RAM. The 16 64-bit, general-purpose, integer registers quadruple the number of general-purpose registers available to applications and device drivers. The 16 128-bit XMM registers double the register space for current SSE/SSE2 (streaming-SIMD-extensions) implementations. Addressing processor-core clock-to-clock improvements, the Athlon 64 includes larger TLB (translation-look-aside buffers) with reduced latencies and improved branch prediction by adding four more bimodal counters in the global-history counter. The Athlon 64 also includes an integrated DDR DRAM controller, HyperTransport interconnects, and large Level 1 and Level 2 caches, so that the Level 2 cache can solely handle large matrices. AMD, www.amd.com.

ADSP-TS201 TIGERSHARC PROCESSOR

Analog Devices’ ADSP-TS201 TigerSHARC processor includes 24 Mbits of embedded DRAM. The DRAM operates at half the core speed, but the memory and cache architecture enable it to effectively operate at the core speed. The input interface to the memory is a 256-bit bus that accesses the six nonhierarchical, interleaved, 4-Mbit memory blocks. Each memory block includes a 128-kbyte SRAM unified cache/buffer array that operates at the full core clock frequency to ensure access to the memory with no latency. The memory structure and interface enable four simultaneous reads or writes during each clock cycle. Using the embedded DRAM enables Analog Devices to quadruple the amount of on-chip memory and maintain the same die area as previous devices that use embedded SRAM. Analog Devices, www.analog.com.

ARM1176JZ(F)-S CORE

ARM’s 1176JZ(F)-S core is the first implementation of ARM’s IEM (Intelligent Energy Manager) and Trustzone technologies. The IEM technology combines hardware and software to balance the processor workload with as much as 25% better systemwide power efficiency. IEM standardizes the processor-performance interface, specifies hardware counters for work measurement, and includes operating-system and application-level algorithms to predict the performance requirements for concurrently operating applications. The software component enables a further layer of control because it can consolidate the results of multiple algorithms and derive an energy-allocation scheme across the system. The Trustzone technology provides for partitioning a small, trusted code base from the main operating system to mitigate the risk of malevolent software’s exploiting the software weaknesses in complex operating systems to compromise the system. ARM, www.arm.com.

 

SOFTWARE

TIMEMACHINE DEBUGGER

Green Hills Software’s TimeMachine debugger enables developers for the first time to step and run applications in reverse at the source-code level and to inspect past variable and register values. This feature enables a developer to backtrack from the manifestation of an application error to identify the root cause of the error. The TimeMachine debugger operates nonintrusively by working with the real-time trace that the Green Hills SuperTrace Probe captures. The probe has 1 Gbyte of trace memory that can capture several hundred million instructions. The TimeMachine also works with Green Hills Software’s instruction set and RTOS simulators. Green Hills Software, www.ghs.com.

CODE COMPOSER STUDIO VERSION 2.2

Texas Instruments’ Code Composer Studio Version 2.2 includes faster simulation technology and four new analysis tools for TMS320C5000 and TMS320C6000 DSP platforms. The simulators exploit the characteristic loops of DSP code by once decoding the target code and executing it multiple times. They also use higher level abstractions to avoid modeling parts of the target, such as the datapath of caches, that a user cannot directly see. These techniques allow a behavioral simulator to process 20 GSM-EFR (speech-transcoder) frames in 15 sec and the TMS320C6416 device simulator to process the same 20 frames in less than 60 sec. The analysis tools include an on-chip cache-memory conflict analyzer, a pipeline-stall analyzer, a code-coverage analyzer, and a multievent function profiler. Texas Instruments, www.ti.com.

POWER MANAGEMENT FRAMEWORK

QNX’s Power Management Framework provides a flexible mechanism to address device and application-specific performance constraints and controls power consumption. The framework differs from general-purpose computing power management standards, such as APM and ACPI, by moving power management from the operating system into a user-customizable application that acts as a centralized power manager. A system designer can implement a power policy that encompasses all of the subsystems and applications to negotiate appropriate power-state changes for each scenario. The framework includes a mechanism for the power manager to query applications to ensure that peripherals that support guaranteed response times are not inappropriately powered down. QNX, www.qnx.com.

 

TEST AND MEASUREMENT

LABVIEW 7 EXPRESS GRAPHICAL DEVELOPMENT ENVIRONMENT

The LabView environment for test, measurement, and control applications features 38 Express interactive VIs (virtual instruments) that deliver advanced measurement functions in easy-to-configure dialogue boxes. With Express VIs, engineers can create applications outside their area of expertise with just a few mouse clicks. This software brings graphical programming to new application areas: Engineers can configure FPGAs using LabView without specialized knowledge of hardware programming languages. In addition, engineers can port their LabView applications to a PDA, making handheld LabView data-acquition systems available for the first time. National Instruments, www.ni.com.

TDS7704B DPO (DIGITAL PHOSPHOR OSCILLOSCOPE)

The Tektronix TDS7704B DPO (Digital Phosphor Oscilloscope) combines features such as a 7-GHz bandwidth, a SiGe (silicon-germanium)-based triggering system, and powerful data-acquisition and -analysis capabilities. The dedicated triggering IC is the first SiGe triggering component and features trigger jitter as narrow as 1 psec rms and glitch detection on the circuit as low as 110 psec. It can trigger on both the rising and the falling edges of a signal to better detect events whose state is indeterminate. In addition, the TDS7704B DPO uses third-generation DPX acquisition technology, a parallel-processing architecture that can dramatically reduce processing time. The TDS7704B DPO also includes a waveform-database-acquisition mode that dramatically reduces the time it takes to accrue the millions of cycles’ worth of samples that most compliance tests require. And, a unique MultiView Zoom feature makes it easy to expand localized waveform segments and maintain an overall view of the larger record. Tektronix, www.tektronix.com.

EMISCOPE-II

Featuring patented SIL (solid-immersion-lens) technology and proprietary near-infrared time-resolved photon-counting technology, the EmiScope-II provides transistor-level backside analysis of complex IC designs with both flip-chip and wire-bond packaging technologies. It allows you to measure internal timing and logic activity in minutes. The EmiScope-II provides orders of magnitude faster acquisition time over other imaging- and photon-collection technology and even enables diagnostics of devices fabricated in processes smaller than 90-nm design rules and 1V power. The EmiScope-II provides an industry-leading less-than-0.25-micron image resolution through the silicon backside to enable analysis of device performance at the transistor or cell level. Conventional air-coupled optics, by contrast, have a resolution of only approximately 0.75 micron. It maintains ease of use with a rotating lens turret that can easily switch between a wide, air-coupled 20× magnification for device navigation, a precise 220× SIL magnification for optical-waveform acquisition. Optonics Inc, www.optonics.com.

N4901A SERIALBERT

The 13.5-Gbps N4901A SerialBERT (bit-error-rate tester) is an easy-to-use and comprehensive tester for the wireline-datacom and semiconductor industries, featuring innovations such as: true differential capabilities that allow stimulating and analyzing true differential signals, including low-voltage differential signals and best-in-class signal integrity. Customers need clean data and clock signals to characterize the device under test and not the instrument. The SerialBERT addresses these needs by offering the industry's fastest rise and fall times and lowest intrinsic jitter. The device also offers clock-data recovery at approximately 3, 6, and 10 Gbps. Agilent Technologies, www.agilent.com.

 

START-UPS OF THE YEAR

ALEREON

Alereon is an advocate of UWB (ultrawideband) technology as the basis of wireless personal-area networks and, specifically, of the MBOA (Multiband OFDM Alliance) proposal under consideration by the IEEE 802.15.3a standards group, which will set a UWB standard. A spin-off of UWB pioneer Time Domain Corp, Alereon plans to have an MBOA-based chip set ship in volume by late 2004. The company is planning an implementation that connects TVs, PCs, DVD, players, MP3 players, and other peripherals at speeds in the "hundreds-of-megabits-per-second" range. The company also owns a large portfolio of intellectual property related to MBOS UWB technology. Alereon recently agreed to license critical patents on a royalty-free basis if the IEEE group adopts MBOA as the standard UWB flavor. MBOA has broad support among consumer-electronics and chip vendors, such as Nokia and Texas Instruments, although Motorola has aggressively backed the competing Direct Sequence UWB technology. Alereon, www.alereon.com.

ENTROPIC COMMUNICATIONS

The consumer-electronics industry continues to look for a home-networking panacea—a network that can carry multiple HDTV streams throughout a typical house with no new wires. Wireless LANs are wonderful for computer-centric applications but thus far lack the range and throughput to support the video application. Entropic Communications plans to leverage the cable-TV coax to implement a home network that can carry four or more HDTV streams along with other home-network traffic generated by music streaming, printer sharing, Web access, and e-mail. Many pundits have believed that the splitters users employ extensively to connect cable TV into multiple rooms in many homes prevent the transmission of data between nodes. Entropic claims that its c.LINK technology can transmit data between any two of 16 nodes at a rate of 270 Mbps. The network uses a time-division media-access scheme so that every pair of nodes on a network gets a scheduled slot to use the 270-Mbps link. Entropic has joined with Cisco, Comcast, EchoStar, Matsushita, Motorola, RadioShack, and Toshiba in the MoCA (Multimedia Over Coax Alliance, www.mocalliance.org) to set standards for coax-based home networks. The company claims it will ship its first chips in mid-2004 and expects some end products to emerge by year’s end. Entropic Communications, www.entropic-communication.com.

MOTIA

Wireless communications are wonderful—when they work. In systems such as WiFi (Wireless Fidelity), however, range limitations can frustrate users. Smart antennas provide one way to improve the range of any wireless system. Motia targets building chips that can add smart-antenna technology in a wireless-product design that can double or even quadruple range. Motia’s technology essentially makes an existing antenna into a multielement antenna that improves reception by combining the signals received at each antenna element and adjusting the antenna characteristics to optimize performance as the user moves and the environment changes. The company’s first product, the Javelin chip introduced in December 2003, targets the WiFi market. The company has also announced plans to deploy its beam-forming technology in mobile satellite-TV antennas. The Javelin signal-processing chip connects between the transceiver and the antenna in 802.11a (5-GHz) or 802.11b/g (2.4-GHz) designs and adds the beam-forming capability. With Javelin in an access point but not in a client, the company claims range will double. With Javelin in both access point and client, the company claims range can quadruple. Motia, www.motia.com.

BEST CONTRIBUTED ARTICLES OF 2003

"Single-ended or differential? That is the question," by Mike McTigue, Agilent Technologies, Feb 6, 2003

"Crossing the abyss: asynchronous signals in a synchronous world," by Mike Stein, Paradigm Works, July 24, 2003

"Power-integrity and ground-bounce simulation of high-speed pc boards," by Martin Vogel and Brad Cole, Ansoft Corp, Sept 18, 2003

"The taming of the slew," by Jim Williams, Linear Technology Corp, Sept 25, 2003

"Designing controlled-impedance vias," by Thomas Neu, Texas Instruments, Oct 2, 2003

"Virtual machines and stochastic scheduling simplify wireless design," by Mike Woodward, RadioScape Ltd, Oct 16, 2003

"Powering your core voltage," by Jason Rubadue, National Semiconductor, Nov 27, 2003

"Exploring memory-interface options," by Kannan Srinivasagam, Cypress Semiconductor Corp, Dec 11, 2003