FROM EDN EUROPE: Communications IP adds SPI interface to FPGA
By Graham Prophet -- EDN, December 11, 2003
Lattice Semiconductor has extended its programme of combining high-speed functions for the communications sector with programmable logic with the introduction of its ORSPI4 (Picture).
As you might infer from the serial number, this chip will handle traffic in the SPI (system-packet interface) 4.2 standard; in fact, there are two SPI 4.2 cores, plus four 3.7-Gbps SERDES blocks, an embedded quad-data-rate memory control, and 16,000 elements of FPGA on the chip. SPI 4.2 is increasingly used as a high-speed parallel interface between processing elements running at line speed.
The "hard" IP occupies about one-quarter of the ORSPI4; programmable logic gates and look-up tables (in the ORCA architecture and supported by Lattice tool sets) take up the rest. Pinout resources mean that if you use the SERDES functions, you can use only one of the SPI cores. The device comes in package options with more than 1000 balls, in either a low-power plastic package or a thermally enhanced package that dissipates more than 10W, depending on configuration.
Dynamic timing—adjusting the signal-sampling points on a per-pin basis, set up in a "learning" mode—allows maximum data rates of 450 MHz DDR (900 Mbps). Complete built-in calendar logic supports 256 logical ports with on- and off-chip buffering, and further FIFO interfaces connect to the FPGA array for custom processing. You can select and combine on-chip blocks to perform a range of functions that require SPI; you might use both SPI 4.2 blocks to bring in, process, and bridge traffic to another standard, or you might bring in traffic on one port, perform some manipulation in the FPGA, and send it back out on the other. The part costs $250 (10,000).
Lattice Semiconductor, +44 1932 582941, www.latticesemi.com.
