Synthesizable cores target low power
By Robert Cravotta -- EDN, December 11, 2003
The SC1200 and SC1400 DSP cores are the first members of Starcore’s synthesizable SC1000 family of 16-bit DSP cores. The SC1200 core is a two-MAC (multiple-accumulate), four-issue VLES (variable-length-execution-set) architecture that targets power-efficient applications for portable devices. The SC1400 targets data-intensive applications with four MACs and a six-issue VLES architecture. These cores are fully synthesizable and can target any wafer-fab process variation, including ultralow-leakage processes. Metrowerks (www.metrowerks.com) and Green Hills (www.ghs.com) provide software-development tools for these cores and include support for RTXC, OSE, SmartDSP, and ThreadX operating systems.
The two cores are each available as stand-alone cores or as part of three preintegrated platforms. The primary platform comprises one of the SC1000-family DSP cores and an on-chip emulator that can support real-time debugging through a JTAG interface. The embedded platform adds an AHB (Advanced High-Performance Bus) 2.0-compliant bus master, a 120 level-triggered interrupt-control unit, gated control for dynamic power reduction, and a configurable memory controller that can support an attachable DMA controller. The advanced platform adds a mapped accelerator interface unit that enables you to attach accelerators and other custom memory-mapped hardware to the core, and it expands the memory-controller subsystem with program- and data-cache controllers. All of these platforms are available for immediate licensing ranging from single projects to ASIC licenses.
Starcore, 1-512-682-8500, www.starcore-dsp.com.
