Tool lets you go with the flow
By Gabe Moretti -- EDN, April 29, 2004
The complexity inherent in designing leading-edge ASIC chips requires customers to integrate the various tools into a coherent design flow. EDA vendors have answered this requirement by releasing “flows,” design methods that show their customers how they can productively integrate the tools. Cadence Design Systems’ approach, its optimized Virtuoso custom-design platform, includes a new chip-integration flow, which couples with the newest release of its Virtuoso Chip Editor. By using the platform and the new tool together, designers will be able to perform full-scale physical integration across multiple design domains, including analog, custom digital, RF, memories/arrays, and digital standard cells, from a full custom point of view.
The new flow and Virtuoso Chip Editor provide designers an automated physical-design-integration product—from floorplanning through chip finishing and tape-out. The new chip integration product provides a seamless bidirectional integration path to and from the Cadence Encounter digital-IC-design platform through the OpenAccess database.
Version 3.3 of the Virtuoso Chip Editor further increases layout productivity and includes immediate visual feedback on design-rule violations and advanced connectivity awareness that alerts users of accidental opens and shorts. The new flow and Virtuoso Chip Editor are available on HP, Sun, IBM, and Linux platforms. The detailed, step-by-step flow uses a distributable 15 million-transistor Ethernet switch and process-design kit as the reference design. Price for a one-year license of the Virtuoso Chip Editor starts at $40,000.
Cadence Design Systems Inc, 1-408-943-1234, www.cadence.com.
