FPGA finesses a photolithography flip-flop
By Brian Dipert -- EDN, April 17, 2003
Given that Xilinx based its Spartan FPGAs on the XC4000 architecture and derived Spartan-II from Virtex devices, it doesn't take a rocket scientist to figure out that the company's Spartan-III line is a limited-speed, restricted-gate-count, and plastic-packaged-only variant of the Virtex-II family (see "Programmable logic shipped just in time for the New Year," EDN, Jan 18, 2001, pg 28). What's surprising about these products isn't their lineage, it's the process that Xilinx builds them on. Conventional semiconductor wisdom says that a company should first use its advanced manufacturing processes to build large and expensive chips whose high prices will cover any cost damage due to periodic yield nosedives. The company moves its lower priced parts to the process only after debugging is complete and yields are high and constant.
Xilinx has turned that logic on its head with Spartan-3, which represents the company's first engagement with 90-nm processing. Mindful of recent reports of 0.13-micron yield problems with Virtex-II Pro at IBM (www.ibm.com), Xilinx is quick to point out that both of its foundry partners, IBM and UMC (www.umc.com), will produce Spartan-3 chips. Is Xilinx ramping Spartan-3 on 90 nm because gate-array ASIC-replacement demand is exploding, as it claims, or because boutique-Virtex-FPGA demand is withering in lock step with the retrenching networking industry, which I suspect is a partial factor? Regardless, you benefit, as long as the 90-nm process is as healthy as Xilinx claims it is.
Befitting their heritage, Spartan-3 chips will include flexible I/O buffers and clock management, embedded multipliers and termination resistors, and other features that premiered in Virtex-II. Table 1 gives product-family features, prices, and anticipated production-availability time frames.
Xilinx, 1-408-559-7778, www.xilinx.com.
