Waiting for X Architecture
Despite delays, diagonal interconnects may finally be nearing production
Jerry Mahoney -- EDN, June 15, 2003
Two years ago this summer, Tokyo, Japan-based electronics giant Toshiba Corp. and an up-and-coming electronic design automation (EDA) company announced a breakthrough semiconductor technology they predicted would lower manufacturing costs, boost performance and reduce power consumption.
Called X Architecture, the technology ran counter to 40 years of IC design by using diagonal circuits to connect transistors on a chip. Previously, chip designers were limited to "Manhattan routing," which resembles a city street map with grids of metal wires running parallel and at right angles to each other. Simplex Solutions Inc., Sunnyvale, CA, developed the first EDA software to create diagonal interconnects that would ultimately let chips run faster. Toshiba, the first chip maker to license the software, predicted that it would be selling the new chips by late last year.
That deadline passed uneventfully, however, and proponents now hope to begin production next year. It's not the first time the laws of physics or the logistics of production have held back a new technology. But it raises the question, What has become of X Architecture?
"Intuitively, X Architecture makes perfect sense," says Ken Rygler, a former executive at DuPont Photomasks Inc., Round Rock, TX, and one of the original proponents of diagonal routing. "But it's been difficult to implement. This is a very hard industry in which to make profound changes, and it's a significant change."
Difficult, perhaps, but far from impossible, say members of the San Jose, CA-based X Initiative, a group of more than a dozen companies created to develop and promote the X Architecture technology. Members include San Jose-based Cadence Design Systems Inc., which bought Simplex last June; Toshiba; DuPont; and semiconductor manufacturing equipment vendors ASML, Nikon and KLA-Tencor.
Ketan Joshi, marketing director for the X Initiative, says that because the shortest route between two points is a straight line, diagonal routing should speed chip performance while reducing the amount of wire needed by 20% and trimming the number of vias, or interconnects between chips' metal layers, by 30%. Diagonal routing, which is to be applied on the fourth and fifth metal layers, is also expected to shrink the size of chips, allowing more circuitry to fit on each silicon wafer.
"You can't rely on optimizing one piece of the supply chain and hoping everything else will work fine."
—Ketan Joshi, marketing director for the X Initiative
Joshi says initiative members demonstrated last year that X Architecture chips could be manufactured with current technology. Geneva, Switzerland-based STMicroelectronics Inc., for instance, has built 130-nanometer chips with diagonal interconnects and is working on a 90-nm test chip. This year, group members plan to produce multiple test chips, using a variety of leading processes. "We see 2004 as a year of production," says Joshi.
Still, X Architecture supporters admit disappointment at the delays in putting the technology into production. Rygler, now president of Austin, TX-based Rygler and Associates Inc., says some momentum was lost when the chip industry became mired in its worst-ever downturn. However, Cadence's acquisition of Simplex did not slow the initiative, says Joshi.
The biggest challenge has been aligning the entire supply chain, from chip designers to makers of photomasks, software and production equipment. All those players need to work in concert to implement X Architecture, and it has taken time to overcome the industry's history of poor communications and find ways for them to work together. "You can't rely on optimizing one piece of the supply chain and hoping everything else will work fine," says Joshi.
"This is a very hard industry in which to make profound changes, and [X Architecture] is a significant change."
—Ken Rygler, former executive at DuPont Photomasks Inc.
Chip designers involved with the initiative, for instance, have had to learn more about the capabilities and limits of the lithography that equipment fabs use to etch their designs onto silicon. "You can no longer just toss designs over the wall," says Rygler. "You have to lay out chip circuitry in a way that is lithographically smart."
Despite such obstacles, supporters believe that the pieces finally are falling into place. "The X Architecture, in building the supply chain, has built the groundwork for a design-for-manufacturing flow," says Rygler. That model, if and when it actually works, may offer the industry efficiencies that go well beyond diagonal interconnects.
Whatever their timetable, X Architecture chips are an idea whose day eventually will come, says Kurt Keutzer, professor of electrical engineering and computer sciences at the University of California, Berkeley. "It's a fundamentally improved approach to doing routing," he says.
Keutzer believes that once the technology proves technically and economically valid, it will sweep the industry. "The way things will go, there will be a small number of leading adopters that pick things up quickly," he says. "I think that over the decade ahead, X Architecture routing will be in the tool set of every designer of high-performance ICs."
