Virtual silicon prototyping targets FPGA designs
By Gabe Moretti -- EDN, September 4, 2003
FPGA designers using the most up-to-date devices must solve a number of new problems, including the inability to achieve performance requirements, unpredictable routing results, routing congestion, tightly packed designs, critical paths spanning various levels of hierarchy, and heavily constrained interconnect wires. Although digital-ASIC designers can now use silicon virtual prototyping to address these problems, FPGA designers have had to solve them using expensive design iterations. To address these problems, Hier Design has introduced its first product, PlanAhead, a hierarchical floorplanner for FPGA designs.
The tool allows designer to quickly inspect the results of placing-and-routing logic blocks on an FPGA fabric. It provides a hierarchical, block-based and incremental design methodology, allowing engineers to incrementally change portions of the design. Working with smaller portions of the design helps engineers to maintain performance requirements, because results of iterative place-and-route functions are often unpredictable, particularly when designers perform them on flattened netlists of the entire chip.
PlanAhead supports the Xilinx Virtex-II and Spartan3 device families. The price for a one-year, time-based license is $25,000. The product is available on Solaris 5.8, Linux 7.3, and Windows XP operating systems.
Hier Design, 1-408-982-8240, www.hierdesign.com.
