Agere, Intel, Others Roll Out New NPU Tech
By Jessica Davis -- EDN, October 21, 2003
Agere, Intel, Motorola, and others will announce new products or improvements to existing ones at this week's Network Processors Conference.
Improving the infrastructure underneath today's networks, several vendors this week will roll out new products or technology roadmaps during the Network Processor in San Jose.
Aimed at wireless infrastructure products, Agere announced a coprocessor to enhance the performance of network processors. The APP100 for Asynchronous Transfer Mode (ATM) processes voice signals at speeds of up to 622Mbits/sec., four times faster than competitors' stand alone chips, according to the Allentown, Pa.-based company. In addition, the chip can simultaneously process 32,000 voice channels, eight times more than competing stand alone chips.
"If you want high performing network processing you need high performing ATM," said Altaf Hussain, manager for network processors and switching solutions at Agere. "Competitors tend to implement this in software. But it's not a scalable solution if you do it in software. By using a separate chip you free up network processor to do more functions faster."
The APP100 reduces the number of chips required because it communicates directly with the network process without relying on a bridge chip. Other products that compete with Agere's coprocessor require three chips to perform the same functions as the APP100, according to Agere. The APP100 is sold together with the APP 500 5Gbits/sec. network processor chip.
"Agere's approach of building a chip designed for voice-over-ATM contrasts with Agere's key competitors who attempt to do all AAL2 functions in software on a network processor," said Linley Gwennap, principal analyst of the Linley Group, in a statement. "This software approach uses a significant portion of the processor's capabilities, leaving less room to perform other functions."
Also at Network Processor Forum, Motorola will introduce today a new member to its PowerQUICC III family of integrated communications processors designed for networking applications such as VPNs, routers, Ethernet switching, and others. Based on the PowerPC core, the MPC8555 offers integrated security and 256 KB of Level 2 cache.
The chip offers a security core that is capable of single-pass encryption and authentication that is required by security protocols such as IPSec, SSL and 802.11i, Motorola said in a statement. The product will be sampled in Q2 2004.
Burlington, Mass.-based start-up Xelerated Inc. today announced its second generation network processor, the X11, offering the equivalent of 360 logical processors. Implemented in .13 microns, the 20 Gbps network processor offers a data flow pipeline that raises performance by 80 percent over the first generation product.
The X11 is designed to bring high function, low cost and programmability to midrange enterprise and low end metro Ethernet designs, the company said in a statement Xelerated will sample the product in Q3 2004. Beyond the single chip level, IBM will discuss new details of its Power PRS 5G switch fabric. Big Blue will offer information on how the fabric can be used for meshed switching in small capacity systems that require QoS features.
Beyond the single chip level, AMCC will discuss new details of its Power PRS 5G switch fabric it recently acquired from IBM. AMMC will offer information on how the fabric can be used for meshed switching in small capacity systems that require QoS features.On the development side, Intel will provide details about its new advanced C compiler for the IXP2XXX NPUs, including a how technology can automatically partition code among multiple processing elements.
The Network Processing Forum runs through Thursday of this week.
