Dedicated processor manages 128 pseudo-wires
By Nicholas Cravotta -- EDN, December 25, 2003
Zarlink Semiconductor has announced the ZL50130, a single-chip Ethernet pseudo-wire processor for data services based on the industry's newest IP (Internet Protocol)/Ethernet draft standard from the IETF (Internet Engineering Task Force) (Picture). The PWE3 (Pseudo-Wire Emulation Edge-to-Edge) Working Group drafted this emerging standard, which uses virtual-LAN connections, called pseudo-wire connections, for transparently tunneling Layer 2 traffic, such as Ethernet, across IP or MPLS (Multi-Protocol Label Switching)-based packet-switched networks. The IETF should adopt the standard, now in its final review stage, in 2004.
LANs and PSNs (packet-switched networks) operate as separate entities whose junction points require network administrators to carefully manage them. For example, managers must regularly update PSN routers to reflect changing LAN profiles, such as IP-address additions and deletions, and PSN traffic requires special handling on the enterprise side. Pseudo-wire services reduce management costs by eliminating time-consuming router updates and enabling users to manage multisite LANs as single networks. By providing a single-network framework for LAN-data transport over Ethernet equipment, service providers can deliver more cost-effective data services over a wider range of bandwidth options than those available today using leased lines or VPNs (virtual private networks).
The processor encapsulates as many as 128 edge-to-edge, wire-speed Fast Ethernet frames, including maximum-sized frames, into IP or MPLS packets and transports them through a packet-switched network over pseudo-wires for reconstruction at the destination point. Users can route traffic from a LAN across one pseudo-wire or split the traffic across multiple connections based on source and destination addresses, allowing network managers to use pseudo-wire services to interconnect multiple sites over one LAN. The device has two Fast Ethernet ingress ports, traffic from which is aggregated onto one Fast Ethernet output. Advanced on-chip quality-of-service mechanisms, such as weighted fair queuing and strict priority, support as many as four classes of service. The device includes sufficient onboard SRAM to support most PWE3 applications without the need for external memory.
The device targets use in a range of network-edge equipment, including switches, routers, and integrated access devices. Additionally, when you couple the device with Ethernet-switch devices, you can aggregate multiple inputs with rate control. The processor complies with the Martini draft standard for Ethernet pseudo-wires.
Now in production, the processor comes in a 552-pin PBGA package. A reference design and an evaluation board are also available. Price is $62.50 (1000). For complete product information, including data sheet, application notes, documentation, and models, visit http://products.zarlink.com/profiles/ZL50130.
Zarlink Semiconductor Inc, 1-613-592-0200, www.zarlink.com.
