Spec clarifications may expand candidate catalog
By Brian Dipert -- EDN, April 17, 2003
Toshiba was troubled when it saw the meager reliability specifications its partner M-Systems was quoting for non-EDAC-fortified NAND-flash memory (see "Flash memory anticipates architecture transformation," EDN, Feb 20, 2003, pg 18). After comparing notes, M-Systems agrees that it may have understated "raw" NAND-flash-memory capabilities. For example, Toshiba tested 80 pieces of its SLC (single-level-cell), 256-Mbit flash memories through 1000 checkerboard-array-pattern-program-then-erase cycles and logged 39 bit errors. This result translates to a bit error for every 34.8 Gbytes of written data, almost 90,000 times better than M-Systems' claimed best-case SLC NAND-flash-memory reliability without EDAC.
Similarly, Toshiba took its 1-Gbit, MLC (multilevel-cell) NAND-flash memory through program-then-erase cycling and obtained 11 bit errors. This outcome correlates to a bit error for every 12.6 Mbytes or more of written data, at least 35,000 times better than M-Systems' best-case, raw, MLC NAND-flash-memory reliability claim. Why do such significant discrepancies exist between the two companies' numbers? They may reflect Toshiba's enhanced technology understanding; after all, Toshiba is the original developer of NAND-flash memory. They may also result from M-Systems marketing folks' overaggressive promotion of their company's EDAC prowess. Part of the reason, though, may be different usage assumptions.
Toshiba's numbers come without documented temperature- and voltage-test conditions; were they best-case, nominal, or worst-case? Toshiba obtained the SLC numbers over a small sample size of devices and after only 1000 erase cycles. (Errors tend to exponentially increase after the cycle count passes a technology- and process-dependent threshold point.) The MLC data is even more suspect; Toshiba couldn't determine whether it came from more than one device or after more than a single write-then-erase cycle. Toshiba's assumptions remind me of the qualifying statement that auto manufacturers make on fuel economy: "Your mileage may vary."
After reviewing Toshiba's updated specs, you may decide that NAND-flash memory is sufficiently robust for your application, perhaps in conjunction with a simpler, software-based EDAC approach than the hardware-centric one M-Systems chose. In this case, take a look at Toshiba's newest NAND-flash memories with altered chip-select logic. The company originally envisioned that there would always be a memory controller between the CPU and the flash memory, so the original NAND bus interface required that chip select be active throughout the lengthy, 25-µsec delay between when the CPU issues a random read command and when the flash memory supplies the data. Toshiba's latest "chip-enable-don't-care" chips remove this restriction, enabling the CPU to access other devices connected to its external bus during the flash memory's "read-busy" delay. The $7 (100), 128-Mbit TC581282AXB and $12 (100), 256-Mbit TC58-2562AXB are now in production, and Toshiba plans to offer five- and six-device, multidie packages containing various combinations of NAND- and NOR-flash memory, SRAM, and PSRAM.
Toshiba, 1-949-455-2000, www.chips.toshiba.com.
