Short-term detour, or long-term bypass?
By Brian Dipert, Technical Editor -- EDN, May 29, 2003
In its promotional materials for the Grand Prix, Pontiac claims that the automobile's tires exemplify that "wider is better." Clearly, cars and computers are different creatures, because buses in and around PCs and embedded systems created from PC building blocks are becoming ever narrower and, correspondingly, ever faster. AMD's HyperTransport, Intel's Hub Interface, Rambus' RaSer, and other high-speed serial and few-pin, logic-to-logic protocols are replacing proprietary parallel configurations. Serial and few-bit variants of PCI Express will sooner or later obsolete 32- and 64-bit PCI, and a 16-bit version of PCI Express is also due to supersede 32-bit AGP during this decade.
SATA (Serial ATA) and the SATA-derived Serial Attached SCSI are beginning to usurp traditional mass-storage interfaces, such as Parallel ATA and SCSI. Similarly serial upstarts, such as Bluetooth for low-bandwidth wireless links, USB Version 1 for moderate-bandwidth needs, and IEEE 1394 and USB Version 2 for highest performance requirements, are superseding legacy parallel-system-to-peripheral buses, such as LPT and SCSI. And, for system-to-system connections, wired and 802.11 wireless-Ethernet connections reign supreme.
The era of the wide, slow; noisy; and pin-count-, power-, and die-area-hungry bus is drawing to a close. Or is it? One notable stubborn stalwart, the memory interface, seems determined to cling to the "wider-is-better" approach, even after a brief flirtation with a narrow-bus suitor. Intel's 865 and 875 chip sets mark the end of the company's Rambus experiment and return Intel to an SDR and DDR-SDRAM path that the rest of the industry has never strayed from (Reference 1). The impact on pin count of this redirection is significant: Intel's dual-16-bit-channel, RDRAM-based i850E chip-set north-bridge device was available in a 615-pin package, whereas the dual-64-bit-channel DDR SDRAM-based i875 north-bridge chip requires a whopping total of 1005 pins. The wide-bus embrace is even stronger in the graphics world; latest generation chips from companies such as ATI Technologies and Nvidia employ 256-bit, double-data-rate memory buses running at near-500-MHz clock rates.
What's unclear is the degree to which RDRAM's banishment from the PC architecture reflects fundamental technical roadblocks with the few-pin approach, versus more nebulous—though no less important—business issues deriving from patent portfolios, R&D budgets, and royalty payments. The serializer/deserializer conversions that both memory controllers and memory chips require clearly incur additional performance overhead. Packet-based protocols and pipe-lined address and data buses have potential efficiency losses, too, though carefully crafted software, controller hardware that reduces access randomness, and beefy on-chip caches to hide the randomness that remains can minimize these effects.
Are these issues merely speed bumps on the path to a serial-memory future or impenetrable barricades? When, if ever, will the issues associated with making parallel memory buses wider and faster grow to the point at which the narrow-bus revolution is more feasible than continued wide-bus evolution? Rambus, with its next-generation Yosemite memory interface under development, is showing its "serial-sooner-or-later" card, but it's keeping the parallel Redwood bus in its back pocket just in case the game continues in an unfavorable direction. And cost-competitive, high-density DRAM embedded within ASICs, no longer a joker but still something of a wild card, is the ace of spades that every memory user is hoping some vendor will eventually toss on the pile. I welcome your feedback on how you see you hand playing out.
Contact me at bdipert@edn.com.
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