Timing analyzer is always a critic
By Gabe Moretti -- EDN, March 20, 2003
Most design teams currently rely on static-timing analysis to ensure timing closure for their designs. Yet, many of the effects that impact signal propagation are dynamic or result from dynamic behavior. To ensure that a circuit works, static-timing models must be pessimistic, so that the static-timing-analysis tools cover the dynamic behavior. This approach often results in safe and conservative but not optimal implementations. Once designers use 130-nm or smaller process technologies, such approximations become unacceptable. You instead have to use some form of dynamic analysis. Although transistor-level tools, such as Spice and its fast-Spice variants, have been around for years, the new designs' sizes exceed the computing capabilities of these tools.
To address this problem Nassda has released Critic, a full-chip critical timing analyzer for postlayout verification of cell-based digital ICs, including their associated clock networks. The product complements static-timing-analysis-verification methods. For analysis of the system clock, Critic automatically identifies the clock net from the device pins, back-annotates the clock net with interconnect RC parasitics, and sets control signals to sensitize the clock paths. The tool then simulates the clock nets with the Spice model for each cell, including precise fan-out loading. Finally, it compares the clock-pin delays with those that a static-analysis tool reports. Critic also automatically analyzes critical paths that the chip designer chooses, usually from a report that the static-timing tool generates.
After a designer invokes analysis, Critic automatically handles the subsequent steps, including back-annotation of postlayout parasitics, which can dramatically affect the timing of critical paths in nanometer designs. Additionally, Critic can automatically include secondary loads to these paths to account for capacitance and other loading effects. After analyzing the design, Critic tests the side-branch values to enable or sensitize the critical paths and creates input patterns for dynamic simulation of the paths.
Unlike approaches that require a Spice simulation run for each path to be analyzed, Critic simultaneously simulates all paths, reducing the number of simulation licenses you need for analysis. During this simulation, Critic uses the Spice model for each cell in each simulated path. Finally, Critic compares the path delays with those reported by a static-analysis tool and provides the designer with a detailed report on timing differences between those results and Critic's results. Using this data, designers can fix timing problems and selectively optimize signal or clock nets for maximum performance.
The tool runs on Sun Solaris, HP-UX, Windows XP/NT/2000, and Linux platforms. The price for a time-based license starts at $65,000.
Nassda Corp, 1-408-562-9168, www.nassda.com.
